opt back to single LZD

Author: WilliamZhang20

src/PE.v

@@ -25,7 +25,6 @@ module PE (
     wire prod_sign = sign_a ^ sign_b;
     wire [7:0] mant_prod = mant_a * mant_b;   // 4×4 = 8-bit product
 
-    localparam signed BIAS = -7;
     localparam FRAC_BITS = 8;
 
     // Simplified exponent calculation (reuse adder)

src/normalize_fp.v

@@ -17,19 +17,8 @@ module int18_to_bf16_lzd #(
     assign sign = acc[17];
     assign mag = sign ? -acc : acc;
 
-    // ===================== HIERARCHICAL LEADING ZERO DETECTOR =====================
-    wire [2:0] lz_hi, lz_mid, lz_lo;
-    wire nz_hi, nz_mid, nz_lo;
-    
-    lzd6 lzd_hi  (.x(mag[17:12]), .lz(lz_hi),  .nz(nz_hi));
-    lzd6 lzd_mid (.x(mag[11:6]),  .lz(lz_mid), .nz(nz_mid));
-    lzd6 lzd_lo  (.x(mag[5:0]),   .lz(lz_lo),  .nz(nz_lo));
+    lzd18 lzd_inst (.x(mag), .lz(lz));
 
-    assign lz = nz_hi  ? {2'b00, lz_hi} :
-                nz_mid ? 5'd6 + {2'b00, lz_mid} :
-                nz_lo  ? 5'd12 + {2'b00, lz_lo} :
-                         5'd18;
-    
     assign exp_unbiased = 9'(17) - 9'(lz) - 9'(FRAC_BITS);
 
     assign normalized = mag << lz;
@@ -54,23 +43,32 @@ module int18_to_bf16_lzd #(
     end
 endmodule
 
-// ===================== 6-BIT LEADING ZERO DETECTOR =====================
-module lzd6 (
-    input  wire [5:0] x,
-    output reg  [2:0] lz,
-    output wire nz  // Non-zero flag
+module lzd18 (
+    input  wire [17:0] x,
+    output reg  [4:0] lz // 5-bit output for 0 to 18
 );
-    assign nz = |x;
 
     always @(*) begin
         casez (x)
-            6'b1?????: lz = 3'd0;
-            6'b01????: lz = 3'd1;
-            6'b001???: lz = 3'd2;
-            6'b0001??: lz = 3'd3;
-            6'b00001?: lz = 3'd4;
-            6'b000001: lz = 3'd5;
-            default:   lz = 3'd6;
+            18'b1?????????????????: lz = 5'd0;
+            18'b01????????????????: lz = 5'd1;
+            18'b001???????????????: lz = 5'd2;
+            18'b0001??????????????: lz = 5'd3;
+            18'b00001?????????????: lz = 5'd4;
+            18'b000001????????????: lz = 5'd5;
+            18'b0000001???????????: lz = 5'd6;
+            18'b00000001??????????: lz = 5'd7;
+            18'b000000001?????????: lz = 5'd8;
+            18'b0000000001????????: lz = 5'd9;
+            18'b00000000001???????: lz = 5'd10;
+            18'b000000000001??????: lz = 5'd11;
+            18'b0000000000001?????: lz = 5'd12;
+            18'b00000000000001????: lz = 5'd13;
+            18'b000000000000001???: lz = 5'd14;
+            18'b0000000000000001??: lz = 5'd15;
+            18'b00000000000000001?: lz = 5'd16;
+            18'b000000000000000001: lz = 5'd17;
+            default:                lz = 5'd18; // All zeros
         endcase
     end
 endmodule