From 11f6232fcb6f7f26738ee1e402563b251048852d Mon Sep 17 00:00:00 2001 From: user3345 <81963672+genan2003@users.noreply.github.com> Date: Tue, 16 Sep 2025 16:17:25 +0300 Subject: [PATCH 1/2] feat: Add LPC55 support files and core modifications Signed-off-by: user3345 <81963672+genan2003@users.noreply.github.com> --- boards/README.md | 1 + boards/lpc55s69-evk/.cargo/config.toml | 14 + boards/lpc55s69-evk/Cargo.toml | 25 + boards/lpc55s69-evk/Makefile | 45 + boards/lpc55s69-evk/README.md | 42 + boards/lpc55s69-evk/chip_layout.ld | 24 + boards/lpc55s69-evk/layout.ld | 6 + boards/lpc55s69-evk/src/io.rs | 67 + boards/lpc55s69-evk/src/main.rs | 305 + chips/Cargo.toml | 339 + chips/lpc55s6x/Cargo.toml | 17 + chips/lpc55s6x/README.md | 9 + chips/lpc55s6x/src/chip.rs | 149 + chips/lpc55s6x/src/clocks.rs | 164 + chips/lpc55s6x/src/ctimer0.rs | 483 + chips/lpc55s6x/src/gpio.rs | 578 + chips/lpc55s6x/src/inputmux.rs | 263 + chips/lpc55s6x/src/interrupts.rs | 54 + chips/lpc55s6x/src/iocon.rs | 4322 +++++ chips/lpc55s6x/src/lib.rs | 122 + chips/lpc55s6x/src/nvic.rs | 23358 +++++++++++++++++++++++ chips/lpc55s6x/src/pint.rs | 587 + chips/lpc55s6x/src/rtc.rs | 186 + chips/lpc55s6x/src/syscon.rs | 3106 +++ 24 files changed, 34266 insertions(+) create mode 100644 boards/lpc55s69-evk/.cargo/config.toml create mode 100644 boards/lpc55s69-evk/Cargo.toml create mode 100644 boards/lpc55s69-evk/Makefile create mode 100644 boards/lpc55s69-evk/README.md create mode 100644 boards/lpc55s69-evk/chip_layout.ld create mode 100644 boards/lpc55s69-evk/layout.ld create mode 100644 boards/lpc55s69-evk/src/io.rs create mode 100644 boards/lpc55s69-evk/src/main.rs create mode 100644 chips/Cargo.toml create mode 100644 chips/lpc55s6x/Cargo.toml create mode 100644 chips/lpc55s6x/README.md create mode 100644 chips/lpc55s6x/src/chip.rs create mode 100644 chips/lpc55s6x/src/clocks.rs create mode 100644 chips/lpc55s6x/src/ctimer0.rs create mode 100644 chips/lpc55s6x/src/gpio.rs create mode 100644 chips/lpc55s6x/src/inputmux.rs create mode 100644 chips/lpc55s6x/src/interrupts.rs create mode 100644 chips/lpc55s6x/src/iocon.rs create mode 100644 chips/lpc55s6x/src/lib.rs create mode 100644 chips/lpc55s6x/src/nvic.rs create mode 100644 chips/lpc55s6x/src/pint.rs create mode 100644 chips/lpc55s6x/src/rtc.rs create mode 100644 chips/lpc55s6x/src/syscon.rs diff --git a/boards/README.md b/boards/README.md index 1df3c865ab..31a480b10f 100644 --- a/boards/README.md +++ b/boards/README.md @@ -98,6 +98,7 @@ but the approximate definitions: | [MSP432 Evaluation kit MSP432P401R](msp_exp432p401r/README.md) | ARM Cortex-M4 | MSP432P401R | openocd | custom | No | | [CY8CPROTO-062-4343W](cy8cproto_62_4343_w/README.md) | ARM Cortex-M0+ | PSoC62 | openocd | custom | No | | [Raspberry Pi Pico 2](raspberry_pi_pico_2/README.md) | ARM Cortex-M33 | RP2350 | openocd | openocd | No | +| [LPCXpresso55S69 Development Board](lpc55s69-evk/README.md) | ARM Cortex-M33 | LPC55S6x | probe-rs | probe-rs | No | ### Other diff --git a/boards/lpc55s69-evk/.cargo/config.toml b/boards/lpc55s69-evk/.cargo/config.toml new file mode 100644 index 0000000000..d2588f07d0 --- /dev/null +++ b/boards/lpc55s69-evk/.cargo/config.toml @@ -0,0 +1,14 @@ +# Licensed under the Apache License, Version 2.0 or the MIT License. +# SPDX-License-Identifier: Apache-2.0 OR MIT +# Copyright Tock Contributors 2024. + +include = [ + "../../cargo/tock_flags.toml", + "../../cargo/unstable_flags.toml", +] + +[build] +target = "thumbv8m.main-none-eabi" + +[unstable] +config-include = true diff --git a/boards/lpc55s69-evk/Cargo.toml b/boards/lpc55s69-evk/Cargo.toml new file mode 100644 index 0000000000..ee101844be --- /dev/null +++ b/boards/lpc55s69-evk/Cargo.toml @@ -0,0 +1,25 @@ +# Licensed under the Apache License, Version 2.0 or the MIT License. +# SPDX-License-Identifier: Apache-2.0 OR MIT +# Copyright Tock Contributors 2025. + +[package] +name = "lpc55s69-evk" +version.workspace = true +authors.workspace = true +edition.workspace = true +build = "../build.rs" + +[dependencies] +cortexm33 = { path = "../../arch/cortex-m33" } +kernel = { path = "../../kernel"} +lpc55s6x = { path = "../../chips/lpc55s6x" } +components = { path = "../components" } +enum_primitive = { path = "../../libraries/enum_primitive" } +capsules-core = { path = "../../capsules/core" } +capsules-system = { path = "../../capsules/system" } + +[build-dependencies] +tock_build_scripts = { path = "../build_scripts" } + +[lints] +workspace = true diff --git a/boards/lpc55s69-evk/Makefile b/boards/lpc55s69-evk/Makefile new file mode 100644 index 0000000000..84009b97da --- /dev/null +++ b/boards/lpc55s69-evk/Makefile @@ -0,0 +1,45 @@ +# Licensed under the Apache License, Version 2.0 or the MIT License. +# SPDX-License-Identifier: Apache-2.0 OR MIT +# Copyright Tock Contributors 2022. + +# Makefile for building the tock kernel for the NUCLEO-F429ZI platform +# + +include ../Makefile.common + +PROBE_RS=probe-rs + +# The specific chip on the NUCLEO-F429ZI board. +# probe-rs needs this to know what it's flashing. +iCHIP=LPC55S69JBD100 + +APP=/home/pc1/Projects/libtock-c/examples/blink/build/cortex-m7/cortex-m7.tbf +KERNEL=$(TOCK_ROOT_DIRECTORY)/target/$(TARGET)/release/$(PLATFORM).elf +KERNEL_WITH_APP=$(TOCK_ROOT_DIRECTORY)/target/$(TARGET)/release/$(PLATFORM)-app.elf + +# Default target for installing the kernel. +.PHONY: install +install: flash + +# flash-debug is no longer needed as a separate target, but kept for +# compatibility. `make debug` is the new recommended command. +.PHONY: flash-debug +flash-debug: debug + +# Flash the release version of the kernel to the board. +.PHONY: flash +flash: $(TOCK_ROOT_DIRECTORY)target/$(TARGET)/release/$(PLATFORM).elf + $(PROBE_RS) flash --chip $(CHIP) --erase-all $< + +# Flash the debug version and attach an RTT console to view kernel logs. +# This is the recommended command for debugging. +.PHONY: debug +debug: $(TOCK_ROOT_DIRECTORY)target/$(TARGET)/debug/$(PLATFORM).elf + $(PROBE_RS) run --chip $(iCHIP) $< + +# An alias for the default `install` target. +.PHONY: program +program: release + arm-none-eabi-objcopy --set-section-flags .apps=LOAD,ALLOC $(KERNEL) $(KERNEL_WITH_APP) + arm-none-eabi-objcopy --update-section .apps=$(APP) $(KERNEL_WITH_APP) + $(PROBE_RS) run --chip $(iCHIP) $(KERNEL_WITH_APP) diff --git a/boards/lpc55s69-evk/README.md b/boards/lpc55s69-evk/README.md new file mode 100644 index 0000000000..0a64fc424f --- /dev/null +++ b/boards/lpc55s69-evk/README.md @@ -0,0 +1,42 @@ +NXP LPCXpresso55S69 Development Board +====================================== + +For more details about the board [visit the NXP board website](https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK). More details about the chip can be found [here](https://www.nxp.com/products/LPC55S6x) + +## Flashing the kernel + +### Prerequisites + +The primary tool used for flashing this board is `probe-rs`. You will need to install it. The recommended way is using `cargo`, the Rust package manager. More details can be found [here](https://probe.rs/docs/getting-started/installation/) + +```bash +$ cargo install probe-rs +``` + +### Compiling and Flashing + +To compile the Tock kernel and flash it to the board, navigate to the `boards/lpc55s69-evk` directory and run `make flash-debug` or `make flash`. This command compiles the kernel either in debug mode or in release mode and uses `probe-rs` to flash the binary file to the chip. + +```bash +$ make flash-debug + or +$ make flash +``` + +The expected output of the command is looking like this: + +```bash +$ make flash-debug + Finished `dev` profile [optimized + debuginfo] target(s) in 8.95s + text data bss dec hex filename + 409B 32 8220 12350 303e /home/USER/tock/target/thumbv8em.main-none-eabihf/debug/lpc55s69-evk +0b7602b822e4507274cd6dd2a47879cee487d8981b83186a9931adc2269880bf /home/USER/tock/target/thumbv8em.main-none-eabihf/debug/lpc55s69-evk.bin +probe-rs run --chip LPC55S69JBD100 /home/USER/tock/targetthumbv8m.main-none-eadihf/debug/lpc55s69-evk.elf +``` + +### Flashing app + +Applications are built separately from the main project. After building an application, specify its path in the `APP` variable within the Makefile, then execute: +```bash +$ make program +``` diff --git a/boards/lpc55s69-evk/chip_layout.ld b/boards/lpc55s69-evk/chip_layout.ld new file mode 100644 index 0000000000..7d462b7f40 --- /dev/null +++ b/boards/lpc55s69-evk/chip_layout.ld @@ -0,0 +1,24 @@ +/* Licensed under the Apache License, Version 2.0 or the MIT License. */ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* Copyright Tock Contributors 2025. */ + +MEMORY +{ + rom(rx) : ORIGIN = 0x00000000, LENGTH = 64K + ram(rwx) : ORIGIN = 0x20000000, LENGTH = 320K + prog(rx) : ORIGIN = 0x00010000, LENGTH = 576K +} + +PAGE_SIZE = 4K; + +SECTIONS{ + .stack (NOLOAD) : +{ + . = ALIGN(8); + *(.stack*) + . = ALIGN(8); +} > ram + +} + +ENTRY(initialize_ram_jump_to_main) diff --git a/boards/lpc55s69-evk/layout.ld b/boards/lpc55s69-evk/layout.ld new file mode 100644 index 0000000000..4faba3611b --- /dev/null +++ b/boards/lpc55s69-evk/layout.ld @@ -0,0 +1,6 @@ +/* Licensed under the Apache License, Version 2.0 or the MIT License. */ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* Copyright Tock Contributors 2025. */ + +INCLUDE ./chip_layout.ld +INCLUDE tock_kernel_layout.ld diff --git a/boards/lpc55s69-evk/src/io.rs b/boards/lpc55s69-evk/src/io.rs new file mode 100644 index 0000000000..232e6e8e26 --- /dev/null +++ b/boards/lpc55s69-evk/src/io.rs @@ -0,0 +1,67 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use crate::{LPCPin, CHIP, PROCESSES, PROCESS_PRINTER}; +use core::fmt::Write; +use core::panic::PanicInfo; +use core::ptr::{addr_of, addr_of_mut}; +// use cortex_m_semihosting::hprint; +use kernel::debug::{self, IoWrite}; +use kernel::hil::gpio::Configure; +use kernel::hil::led::LedHigh; +use lpc55s6x::gpio::GpioPin; +use lpc55s6x::iocon::{Config, Function, Iocon, Pull, Slew}; + +pub struct Writer; + +/// Global static for debug writer +pub static mut WRITER: Writer = Writer; + +// TODO: This will be implemented later, when UART support will be available + +impl Write for Writer { + fn write_str(&mut self, s: &str) -> ::core::fmt::Result { + for _byte in s.as_bytes() { + // TODO print one character when UART becomes available + } + Ok(()) + } +} + +impl IoWrite for Writer { + fn write(&mut self, buf: &[u8]) -> usize { + for _byte in buf { + // TODO print one character when UART becomes available + } + buf.len() + } +} + +#[panic_handler] +pub unsafe fn panic_fmt(panic_info: &PanicInfo) -> ! { + let iocon_ctrl = Iocon::new(); + let led_pin_config = Config { + function: Function::GPIO, + pull: Pull::Up, + slew: Slew::Standard, + invert: false, + digital_mode: true, + open_drain: false, + }; + iocon_ctrl.configure_pin(LPCPin::P1_6, led_pin_config); + let red_led = GpioPin::new(LPCPin::P1_6); + red_led.make_output(); + let led = &mut LedHigh::new(&red_led); + let writer = &mut *addr_of_mut!(WRITER); + + debug::panic( + &mut [led], + writer, + panic_info, + &cortexm33::support::nop, + PROCESSES.unwrap().as_slice(), + &*addr_of!(CHIP), + &*addr_of!(PROCESS_PRINTER), + ) +} diff --git a/boards/lpc55s69-evk/src/main.rs b/boards/lpc55s69-evk/src/main.rs new file mode 100644 index 0000000000..81cee12a59 --- /dev/null +++ b/boards/lpc55s69-evk/src/main.rs @@ -0,0 +1,305 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +#![no_std] +#![no_main] + +mod io; + +use capsules_core::virtualizers::virtual_alarm::VirtualMuxAlarm; +use components::led::LedsComponent; +use kernel::component::Component; +use kernel::hil::led::LedLow; +use kernel::platform::{KernelResources, SyscallDriverLookup}; +use kernel::process::ProcessArray; +use kernel::scheduler::round_robin::RoundRobinSched; +use kernel::{capabilities, create_capability, static_init}; +use lpc55s6x::chip::{Lpc55s69, Lpc55s69DefaultPeripheral}; +use lpc55s6x::clocks::Clock; +use lpc55s6x::gpio::{GpioPin, LPCPin}; +use lpc55s6x::pint::Edge; + +#[no_mangle] +#[link_section = ".stack_buffer"] +pub static mut STACK_MEMORY: [u8; 0x4000] = [0; 0x4000]; + +static mut PROCESS_PRINTER: Option<&'static capsules_system::process_printer::ProcessPrinterText> = + None; + +fn system_init() { + let clocks = Clock::new(); + clocks.start_gpio_clocks(); + clocks.start_timer_clocks(); +} + +unsafe fn get_peripherals() -> &'static mut Lpc55s69DefaultPeripheral<'static> { + static_init!(Lpc55s69DefaultPeripheral, Lpc55s69DefaultPeripheral::new()) +} + +const FAULT_RESPONSE: capsules_system::process_policies::PanicFaultPolicy = + capsules_system::process_policies::PanicFaultPolicy {}; + +// Number of concurrent processes this platform supports. +const NUM_PROCS: usize = 4; + +/// Static variables used by io.rs. +static mut PROCESSES: Option<&'static ProcessArray> = None; +static mut CHIP: Option<&'static Lpc55s69> = None; + +pub struct Lpc55s69evk { + alarm: &'static capsules_core::alarm::AlarmDriver< + 'static, + VirtualMuxAlarm<'static, lpc55s6x::ctimer0::LPCTimer<'static>>, + >, + gpio: &'static capsules_core::gpio::GPIO<'static, lpc55s6x::gpio::GpioPin<'static>>, + led: &'static capsules_core::led::LedDriver<'static, LedLow<'static, GpioPin<'static>>, 1>, + button: &'static capsules_core::button::Button<'static, lpc55s6x::gpio::GpioPin<'static>>, + scheduler: &'static RoundRobinSched<'static>, + systick: cortexm33::systick::SysTick, +} + +impl SyscallDriverLookup for Lpc55s69evk { + fn with_driver(&self, driver_num: usize, f: F) -> R + where + F: FnOnce(Option<&dyn kernel::syscall::SyscallDriver>) -> R, + { + match driver_num { + // capsules_core::console::DRIVER_NUM => f(Some(self.console)), + capsules_core::alarm::DRIVER_NUM => f(Some(self.alarm)), + capsules_core::led::DRIVER_NUM => f(Some(self.led)), + capsules_core::button::DRIVER_NUM => f(Some(self.button)), + capsules_core::gpio::DRIVER_NUM => f(Some(self.gpio)), + _ => f(None), + } + } +} + +impl KernelResources>> for Lpc55s69evk { + type SyscallDriverLookup = Self; + type SyscallFilter = (); + type ProcessFault = (); + type Scheduler = RoundRobinSched<'static>; + type SchedulerTimer = cortexm33::systick::SysTick; + type WatchDog = (); + type ContextSwitchCallback = (); + + fn syscall_driver_lookup(&self) -> &Self::SyscallDriverLookup { + self + } + fn syscall_filter(&self) -> &Self::SyscallFilter { + &() + } + fn process_fault(&self) -> &Self::ProcessFault { + &() + } + fn scheduler(&self) -> &Self::Scheduler { + self.scheduler + } + fn scheduler_timer(&self) -> &Self::SchedulerTimer { + &self.systick + } + fn watchdog(&self) -> &Self::WatchDog { + &() + } + fn context_switch_callback(&self) -> &Self::ContextSwitchCallback { + &() + } +} + +#[no_mangle] +unsafe fn main() -> ! { + cortexm33::scb::set_vector_table_offset(core::ptr::null::<()>()); + + system_init(); + + let peripherals = get_peripherals(); + + peripherals.pins.init(); + + let chip = static_init!( + Lpc55s69, + Lpc55s69::new(peripherals) + ); + + cortexm33::nvic::enable_all(); + + let processes = components::process_array::ProcessArrayComponent::new() + .finalize(components::process_array_component_static!(NUM_PROCS)); + PROCESSES = Some(processes); + let board_kernel = static_init!(kernel::Kernel, kernel::Kernel::new(processes.as_slice())); + + peripherals.ctimer0.init(96_000_000); + + let mux_alarm = components::alarm::AlarmMuxComponent::new(&peripherals.ctimer0).finalize( + components::alarm_mux_component_static!(lpc55s6x::ctimer0::LPCTimer), + ); + + let alarm = components::alarm::AlarmDriverComponent::new( + board_kernel, + capsules_core::alarm::DRIVER_NUM, + mux_alarm, + ) + .finalize(components::alarm_component_static!( + lpc55s6x::ctimer0::LPCTimer + )); + + let gpio = components::gpio::GpioComponent::new( + board_kernel, + capsules_core::gpio::DRIVER_NUM, + components::gpio_component_helper!( + lpc55s6x::gpio::GpioPin, + 0 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_0), + 1 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_1), + 2 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_2), + 3 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_3), + 5 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_4), + 6 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_5), + 7 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_6), + 8 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_7), + 9 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_8), + 10 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_9), + 11 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_10), + 12 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_11), + 13 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_12), + 14 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_13), + 15 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_14), + 16 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_15), + 17 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_16), + 18 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_17), + 19 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_18), + 20 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_19), + 21 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_20), + 22 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_21), + 23 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_22), + 24 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_23), + 25 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_24), + 26 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_25), + 27 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_26), + 28 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_27), + 29 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_28), + 30 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_29), + 31 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_30), + 32 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P0_31), + 33 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_0), + 34 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_1), + 35 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_2), + 36 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_3), + // This is the blue LED: 37 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_4), + 38 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_5), + // 39 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_6), + 40 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_7), + 41 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_8), + //This is the button: 42 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_9), + 43 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_10), + 44 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_11), + 45 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_12), + 46 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_13), + 47 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_14), + 48 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_15), + 49 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_16), + 50 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_17), + 51 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_18), + 52 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_19), + 53 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_20), + 54 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_21), + 55 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_22), + 56 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_23), + 57 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_24), + 58 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_25), + 59 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_26), + 60 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_27), + 61 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_28), + 62 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_29), + 63 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_30), + 64 => peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_31), + ), + ) + .finalize(components::gpio_component_static!(lpc55s6x::gpio::GpioPin)); + + let button_pin = peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_9); + + let button = components::button::ButtonComponent::new( + board_kernel, + capsules_core::button::DRIVER_NUM, + components::button_component_helper!( + GpioPin, + ( + button_pin, + kernel::hil::gpio::ActivationMode::ActiveLow, + kernel::hil::gpio::FloatingState::PullUp + ), + ), + ) + .finalize(components::button_component_static!( + lpc55s6x::gpio::GpioPin + )); + + let led_pin = peripherals.pins.get_pin(lpc55s6x::gpio::LPCPin::P1_4); + + let led = LedsComponent::new().finalize(components::led_component_static!( + LedLow<'static, GpioPin>, + LedLow::new(led_pin) + )); + + const INPUTMUX_SRC: u8 = 41; + + peripherals.pins.inputmux.set_pintsel(0, INPUTMUX_SRC); + + peripherals.pins.pint.configure_interrupt(0, Edge::Rising); + + // These symbols are defined in the linker script. + extern "C" { + /// Beginning of the ROM region containing app images. + static _sapps: u8; + /// End of the ROM region containing app images. + static _eapps: u8; + /// Beginning of the RAM region for app memory. + static mut _sappmem: u8; + /// End of the RAM region for app memory. + static _eappmem: u8; + } + + let process_management_capability = + create_capability!(capabilities::ProcessManagementCapability); + + kernel::process::load_processes( + board_kernel, + chip, + core::slice::from_raw_parts( + core::ptr::addr_of!(_sapps), + core::ptr::addr_of!(_eapps) as usize - core::ptr::addr_of!(_sapps) as usize, + ), + core::slice::from_raw_parts_mut( + core::ptr::addr_of_mut!(_sappmem), + core::ptr::addr_of!(_eappmem) as usize - core::ptr::addr_of!(_sappmem) as usize, + ), + &FAULT_RESPONSE, + &process_management_capability, + ) + .unwrap_or_else(|err| { + kernel::debug!("Error loading processes!"); + kernel::debug!("{:?}", err); + }); + + let main_loop_capability = create_capability!(capabilities::MainLoopCapability); + + let scheduler = components::sched::round_robin::RoundRobinComponent::new(processes) + .finalize(components::round_robin_component_static!(NUM_PROCS)); + + let lpc55 = Lpc55s69evk { + alarm, + gpio, + button, + led, + scheduler, + systick: cortexm33::systick::SysTick::new_with_calibration(12_000_000), + }; + + board_kernel.kernel_loop( + &lpc55, + chip, + None::>.as_ref(), + &main_loop_capability, + ); +} diff --git a/chips/Cargo.toml b/chips/Cargo.toml new file mode 100644 index 0000000000..0799f9b8c0 --- /dev/null +++ b/chips/Cargo.toml @@ -0,0 +1,339 @@ +# Licensed under the Apache License, Version 2.0 or the MIT License. +# SPDX-License-Identifier: Apache-2.0 OR MIT +# Copyright Tock Contributors 2022. + +[workspace] +members = [ + "arch/cortex-m", + "arch/cortex-v7m", + "arch/cortex-m0", + "arch/cortex-m0p", + "arch/cortex-m3", + "arch/cortex-m33", + "arch/cortex-m4", + "arch/cortex-m7", + "arch/riscv", + "arch/rv32i", + "arch/x86", + "boards/nano_rp2040_connect", + "boards/arty_e21", + "boards/opentitan/earlgrey-cw310", + "boards/esp32-c3-devkitM-1", + "boards/cy8cproto_62_4343_w", + "boards/clue_nrf52840", + "boards/veer_el2_sim", + "boards/hail", + "boards/hifive_inventor", + "boards/hifive1", + "boards/imix", + "boards/imxrt1050-evkb", + "boards/lpc55s69-evk", + "boards/litex/arty", + "boards/litex/sim", + "boards/msp_exp432p401r", + "boards/microbit_v2", + "boards/wm1110dev", + "boards/makepython-nrf52840", + "boards/nordic/nrf52840dk", + "boards/nordic/nrf52840_dongle", + "boards/nordic/nrf52dk", + "boards/sma_q3", + "boards/nucleo_f429zi", + "boards/nucleo_f446re", + "boards/particle_boron", + "boards/pico_explorer_base", + "boards/raspberry_pi_pico", + "boards/raspberry_pi_pico_2", + "boards/apollo3/redboard_artemis_atp", + "boards/apollo3/redboard_artemis_nano", + "boards/apollo3/lora_things_plus", + "boards/redboard_redv", + "boards/stm32f3discovery", + "boards/stm32f412gdiscovery", + "boards/stm32f429idiscovery", + "boards/teensy40", + "boards/nano33ble", + "boards/nano33ble_rev2", + "boards/qemu_i486_q35", + "boards/qemu_rv32_virt", + "boards/weact_f401ccu6/", + "boards/configurations/nrf52840dk/nrf52840dk-test-appid-ecdsap256", + "boards/configurations/nrf52840dk/nrf52840dk-test-appid-sha256", + "boards/configurations/nrf52840dk/nrf52840dk-test-appid-tbf", + "boards/configurations/nrf52840dk/nrf52840dk-test-invs", + "boards/configurations/nrf52840dk/nrf52840dk-test-kernel", + "boards/configurations/nrf52840dk/nrf52840dk-test-dynamic-app-load", + "boards/configurations/microbit_v2/microbit_v2-test-dynamic-app-load", + "boards/tutorials/nrf52840dk-root-of-trust-tutorial", + "boards/tutorials/nrf52840dk-dynamic-apps-and-policies", + "boards/tutorials/nrf52840dk-hotp-tutorial", + "boards/tutorials/nrf52840dk-thread-tutorial", + "capsules/aes_gcm", + "capsules/ecdsa_sw", + "capsules/core", + "capsules/extra", + "capsules/system", + "chips/apollo3", + "chips/arty_e21_chip", + "chips/e310_g002", + "chips/e310_g003", + "chips/e310x", + "chips/earlgrey", + "chips/esp32", + "chips/esp32-c3", + "chips/imxrt10xx", + "chips/lpc55s6x", + "chips/litex", + "chips/litex_vexriscv", + "chips/lowrisc", + "chips/msp432", + "chips/nrf52", + "chips/nrf52832", + "chips/nrf52833", + "chips/nrf52840", + "chips/nrf5x", + "chips/x86_q35", + "chips/qemu_rv32_virt_chip", + "chips/psoc62xa", + "chips/rp2040", + "chips/rp2350", + "chips/sam4l", + "chips/segger", + "chips/sifive", + "chips/stm32f303xc", + "chips/stm32f401cc", + "chips/stm32f429zi", + "chips/stm32f446re", + "chips/stm32f412g", + "chips/stm32f4xx", + "chips/veer_el2", + "chips/virtio", + "kernel", + "libraries/enum_primitive", + "libraries/riscv-csr", + "libraries/tock-cells", + "libraries/tock-register-interface", + "libraries/tickv", +] +exclude = ["tools/"] +resolver = "2" + +[workspace.package] +version = "0.2.3-dev" +authors = ["Tock Project Developers "] +edition = "2021" + +[profile.dev] +panic = "abort" +lto = true +opt-level = "z" +debug = true + +[profile.release] +panic = "abort" +lto = true +opt-level = "z" +debug = true +codegen-units = 1 + +# CLIPPY CONFIGURATION +# +# We first disallow all lints in a particular group, then re-allow each one +# Tock does not comply with or we do not want to use. +# +# For each group there are three sections: +# 1. The first section are lints we don't want with a comment explaining our use +# case for not enabling that lint. +# 2. The second section are lints we may not want, we probably have to see the +# resulting diff. +# 3. The third section are lints that we do want we just need to fixup the code +# to pass the lint checks. +[workspace.lints.clippy] +# RESTRICTION LINTS +restriction = { level = "allow", priority = -1 } +unused_result_ok = "deny" + +# COMPLEXITY LINTS +complexity = { level = "deny", priority = -1 } + +# Subjective, and complex functions may need many arguments. +too_many_arguments = "allow" +# This is pretty sensitive, even `Result`s with returned buffers trigger this. +# It is not worth us creating types for all of these. +type_complexity = "allow" +# We use options extensively and they can be as clear as if let statements. +option_map_unit_fn = "allow" +# Sometimes the semantic meaning of variables means it is more clear to use +# nonminimal if statements, particularly when matching hardware or datasheets. +nonminimal_bool = "allow" +# Particularly for setting register values, expressing a zero offset can be +# semantically meaningful and encourage consistency between several lines of +# code. +identity-op = "allow" +# Subjective, and for SyscallDrivers sometimes enumerating the specific command +# numbers rather than using a range is semantically more clear. +manual-range-patterns = "allow" +# Particularly when interactive with hardware, including a leading zero can +# often be semantically more clear. +zero_prefixed_literal = "allow" + + +manual-flatten = "allow" + + +# STYLE +style = { level = "deny", priority = -1 } + +# Sometimes an if block is standalone and shouldn't be merged with an else. +collapsible_else_if = "allow" +# Multiple if blocks can be clearer to express a particular logical flow. +collapsible_if = "allow" +# Sometimes if statements are easier to read than match statements. +comparison_chain = "allow" +# Sometimes it's more clear to have repetition in enum names. +enum-variant-names = "allow" +# For buffers, `.get(0)` (using byte index) makes more sense than `.first()`. +get_first = "allow" +# There are often good reasons to enumerate different states that have the same +# effect. +if_same_then_else = "allow" +# Buffers and objects can have a length of 0, but it isn't necessarily intuitive +# to think of a buffer or those objects as "empty". +len_without_is_empty = "allow" +# Buffer logic often makes more sense with lengths, and not `is_empty()`. +len_zero = "allow" +# Sometimes the borrow checker works better with `match` instead of `.map()`. +manual-map = "allow" +# Syntax like `!(-17..=4).contains(&x)` is just not clear. +manual_range_contains = "allow" +# Match statement is clear, using `matches!()` is not an improvement. +match_like_matches_macro = "allow" +# Sometimes it makes sense to have module in a folder of the same name. +module_inception = "allow" +# Maybe someday we want this, but right now `for i in 0..4` is much more clear +# than using `.iter()` functions like `.skip(n)`. +needless-range-loop = "allow" +# We don't need unused Default implementations. +new_without_default = "allow" +# Using `Result()` is good practice, even if there is no meaning to the error. +result_unit_err = "allow" +# For hardware registers it can make sense to group bits semantically and not +# just in multiples of four. +unusual-byte-groupings = "allow" +# We widely use upper case acronyms for hardware registers and fields. +upper_case_acronyms = "allow" + + +missing_safety_doc = "allow" +doc_lazy_continuation = "allow" + + +# PERF +perf = { level = "deny", priority = -1 } + +# Tock extensively uses enums for state machines, and it often is much clearer +# to store objects between states in the state enum rather than as "global" +# variables in the struct itself. Therefore, some enums end up quite large. +large-enum-variant = "allow" + + +# CARGO +cargo = { level = "deny", priority = -1 } + +# Tock includes over 100 crates, and it is just too pedantic to expect each one +# to have full and correct metadata. +cargo_common_metadata = "allow" +# We generally avoid all cargo features, and therefore it isn't intuitive that +# we would expect some features to be enabled by default, so it can make sense +# to have a feature to disable something. +negative-feature-names = "allow" + + +# NURSERY +nursery = { level = "deny", priority = -1 } + +# In some cases we mark `pub(crate)` in a module which isn't exposed outside of +# the crate. This redundancy is OK, and if the module were to be made public +# for some reason in the future the visibility would transparently change. +redundant_pub_crate = "allow" +# Sometimes a `map_or_else()` seems like a better option, but it doesn't always +# pass the borrow checker. if let/else is more reliable. +option_if_let_else = "allow" +# Some OS functions are necessarily complex. +cognitive_complexity = "allow" + + +unused_peekable = "allow" +branches_sharing_code = "allow" + + +use_self = "allow" +or_fun_call = "allow" +missing_const_for_fn = "allow" +equatable_if_let = "allow" +derive_partial_eq_without_eq = "allow" +empty_line_after_doc_comments = "allow" +trait_duplication_in_bounds = "allow" +useless_let_if_seq = "allow" + + +# PEDANTIC +pedantic = { level = "deny", priority = -1 } + +doc_markdown = "allow" +missing_errors_doc = "allow" +if_not_else = "allow" +cast_sign_loss = "allow" +too_many_lines = "allow" +must_use_candidate = "allow" +manual_let_else = "allow" +single_match_else = "allow" +inline_always = "allow" +module_name_repetitions = "allow" +unnested-or-patterns = "allow" +redundant_else = "allow" +return_self_not_must_use = "allow" +match_same_arms = "allow" +explicit_iter_loop = "allow" +similar_names = "allow" +unnecessary_wraps = "allow" +manual_assert = "allow" +transmute_ptr_to_ptr = "allow" +struct_excessive_bools = "allow" +fn_params_excessive_bools = "allow" +trivially_copy_pass_by_ref = "allow" +borrow_as_ptr = "allow" +tuple_array_conversions = "allow" +verbose_bit_mask = "allow" +large_types_passed_by_value = "allow" +no_mangle_with_rust_abi = "allow" +struct_field_names = "allow" +needless_continue = "allow" + + +cast_lossless = "allow" +cast_possible_truncation = "allow" +cast_precision_loss = "allow" +range_plus_one = "allow" +missing_panics_doc = "allow" +match_wildcard_for_single_variants = "allow" +unused_self = "allow" +cast-possible-wrap = "allow" +uninlined_format_args = "allow" +unreadable_literal = "allow" +needless_pass_by_value = "allow" +items_after_statements = "allow" +ref_option_ref = "allow" +match_bool = "allow" +redundant_closure_for_method_calls = "allow" +no_effect_underscore_binding = "allow" +iter_without_into_iter = "allow" + + +semicolon_if_nothing_returned = "allow" +ptr_as_ptr = "allow" +ptr_cast_constness = "allow" +mut_mut = "allow" +cast_ptr_alignment = "allow" +used_underscore_binding = "allow" +checked_conversions = "allow" diff --git a/chips/lpc55s6x/Cargo.toml b/chips/lpc55s6x/Cargo.toml new file mode 100644 index 0000000000..b4ad1ac38f --- /dev/null +++ b/chips/lpc55s6x/Cargo.toml @@ -0,0 +1,17 @@ +# Licensed under the Apache License, Version 2.0 or the MIT License. +# SPDX-License-Identifier: Apache-2.0 OR MIT +# Copyright Tock Contributors 2025. + +[package] +name = "lpc55s6x" +version.workspace = true +authors.workspace = true +edition.workspace = true + +[dependencies] +cortexm33 = { path = "../../arch/cortex-m33" } +kernel = { path = "../../kernel" } +enum_primitive = { path = "../../libraries/enum_primitive" } + +[lints] +workspace = true diff --git a/chips/lpc55s6x/README.md b/chips/lpc55s6x/README.md new file mode 100644 index 0000000000..1809e86d9b --- /dev/null +++ b/chips/lpc55s6x/README.md @@ -0,0 +1,9 @@ +LPC55S6x +======== + +This crate provides an implementation for the LPC55S6x chip developed by NXP Semiconductors. The chip features a dual-core ARM Cortex-M33 processor, but this implementation utilizes only Core0. + +## Links + +* [General informations](https://www.nxp.com/products/LPC55S6x) +* [Datasheet](https://www.nxp.com/docs/en/data-sheet/LPC55S6x.pdf) diff --git a/chips/lpc55s6x/src/chip.rs b/chips/lpc55s6x/src/chip.rs new file mode 100644 index 0000000000..df2ea345ac --- /dev/null +++ b/chips/lpc55s6x/src/chip.rs @@ -0,0 +1,149 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +#![allow(clippy::elidable_lifetime_names)] +use core::fmt::Write; +use core::panic; + +use cortexm33::{CortexM33, CortexMVariant}; +use kernel::platform::chip::Chip; +use kernel::platform::chip::InterruptService; + +use crate::ctimer0::LPCTimer; +use crate::gpio::Pins; +use crate::interrupts; + +#[repr(u8)] +pub enum Processor { + Processor0 = 0, + Processor1 = 1, +} + +pub struct Lpc55s69<'a, I: InterruptService + 'a> { + mpu: cortexm33::mpu::MPU<8>, + userspace_kernel_boundary: cortexm33::syscall::SysCall, + interrupt_service: &'a I, +} + +impl<'a, I: InterruptService> Lpc55s69<'a, I> { + pub unsafe fn new(interrupt_service: &'a I) -> Self { + Self { + mpu: cortexm33::mpu::new(), + userspace_kernel_boundary: cortexm33::syscall::SysCall::new(), + interrupt_service, + } + } +} + +impl Chip for Lpc55s69<'_, I> { + type MPU = cortexm33::mpu::MPU<8>; + type UserspaceKernelBoundary = cortexm33::syscall::SysCall; + type ThreadIdProvider = cortexm33::thread_id::CortexMThreadIdProvider; + + fn service_pending_interrupts(&self) { + unsafe { + while let Some(interrupt) = cortexm33::nvic::next_pending() { + if !self.interrupt_service.service_interrupt(interrupt) { + panic!("unhandled interrupt {}", interrupt); + } + + let n = cortexm33::nvic::Nvic::new(interrupt); + n.clear_pending(); + n.enable(); + } + } + } + + fn has_pending_interrupts(&self) -> bool { + unsafe { cortexm33::nvic::has_pending() } + } + + fn mpu(&self) -> &Self::MPU { + &self.mpu + } + + fn userspace_kernel_boundary(&self) -> &Self::UserspaceKernelBoundary { + &self.userspace_kernel_boundary + } + + fn sleep(&self) { + unsafe { + cortexm33::support::wfi(); + } + } + + unsafe fn with_interrupts_disabled(&self, f: F) -> R + where + F: FnOnce() -> R, + { + cortexm33::support::with_interrupts_disabled(f) + } + + unsafe fn print_state(&self, writer: &mut dyn Write) { + CortexM33::print_cortexm_state(writer); + } +} + +pub struct Lpc55s69DefaultPeripheral<'a> { + pub pins: Pins<'a>, + pub ctimer0: LPCTimer<'a>, +} + +impl<'a> Lpc55s69DefaultPeripheral<'a> { + pub fn new() -> Self { + Self { + pins: Pins::new(), + ctimer0: LPCTimer::new(), + } + } + + pub fn resolve_dependencies(&'static self) {} +} + +impl<'a> InterruptService for Lpc55s69DefaultPeripheral<'a> { + unsafe fn service_interrupt(&self, interrupt: u32) -> bool { + match interrupt { + interrupts::GPIO_INT0_IRQ0 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ1 => { + self.pins.handle_interrupt(); + true + } + + interrupts::GPIO_INT0_IRQ2 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ3 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ4 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ5 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ6 => { + self.pins.handle_interrupt(); + true + } + interrupts::GPIO_INT0_IRQ7 => { + self.pins.handle_interrupt(); + true + } + + interrupts::CTIMER0 => { + self.ctimer0.handle_interrupt(); + true + } + + _ => true, + } + } +} diff --git a/chips/lpc55s6x/src/clocks.rs b/chips/lpc55s6x/src/clocks.rs new file mode 100644 index 0000000000..c1eae77adf --- /dev/null +++ b/chips/lpc55s6x/src/clocks.rs @@ -0,0 +1,164 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use crate::syscon::{self, SysconRegisters}; +use kernel::utilities::{ + registers::interfaces::{ReadWriteable, Writeable}, + StaticRef, +}; + +// const CLKCTL_BASE: StaticRef = +// unsafe { StaticRef::new(0x4000_2000 as *const ClkctlRegisters) }; + +// const PMC_BASE: StaticRef = +// unsafe { StaticRef::new(0x5000_1000 as *const PmcRegisters) }; + +// const ANACTRL_BASE: StaticRef = +// unsafe { StaticRef::new(0x5000_3000 as *const AnactrlRegisters) }; + +pub const SYSCON_BASE: StaticRef = + unsafe { StaticRef::new(0x40000000 as *const SysconRegisters) }; + +pub enum Peripheral { + Flexcomm0, + Flexcomm1, + Flexcomm2, + Flexcomm3, + Flexcomm4, + Gpio0, + Gpio1, + Dma0, +} + +#[derive(Copy, Clone)] +pub enum FrgClockSource { + MainClock, + SystemPll, + Fro12Mhz, + Fro96Mhz, + Fro1Mhz, + Mclk, + Osc32Khz, + NoClock, +} + +pub struct Clock { + syscon: &'static SysconRegisters, +} + +impl Clock { + pub fn new() -> Clock { + Clock { + syscon: &SYSCON_BASE, + } + } + + pub fn start_gpio_clocks(&self) { + self.syscon.ahbclkctrl0.modify( + syscon::AHBCLKCTRL0::SRAM_CTRL1::SET + + syscon::AHBCLKCTRL0::SRAM_CTRL2::SET + + syscon::AHBCLKCTRL0::SRAM_CTRL3::SET + + syscon::AHBCLKCTRL0::SRAM_CTRL4::SET + + syscon::AHBCLKCTRL0::IOCON::SET + + syscon::AHBCLKCTRL0::GPIO0::SET + + syscon::AHBCLKCTRL0::GPIO1::SET + + syscon::AHBCLKCTRL0::GPIO2::SET + + syscon::AHBCLKCTRL0::GPIO3::SET + + syscon::AHBCLKCTRL0::PINT::SET + + syscon::AHBCLKCTRL0::MUX::SET, + ); + } + + pub fn start_timer_clocks(&self) { + self.syscon + .ctimerclksel0 + .modify(syscon::CTIMERCLKSEL0::SEL::CLEAR); + + self.syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::TIMER0::SET); + + self.syscon.clkoutsel.modify(syscon::CLKOUTSEL::SEL::SET); + } + + pub fn set_frg_clock_source(&self, frg_id: u32, source: FrgClockSource) { + let sel_val = match source { + FrgClockSource::MainClock => syscon::FCCLKSEL::SEL::MainClock, + FrgClockSource::SystemPll => syscon::FCCLKSEL::SEL::SystemPLLDividedClock, + FrgClockSource::Fro12Mhz => syscon::FCCLKSEL::SEL::FRO12MHzClock, + FrgClockSource::Fro96Mhz => syscon::FCCLKSEL::SEL::FRO96MHzClock, + FrgClockSource::Fro1Mhz => syscon::FCCLKSEL::SEL::FRO1MHzClock, + FrgClockSource::Mclk => syscon::FCCLKSEL::SEL::MCLKClock, + FrgClockSource::Osc32Khz => syscon::FCCLKSEL::SEL::Oscillator32KHzClock, + FrgClockSource::NoClock => syscon::FCCLKSEL::SEL::NoClock, + }; + + match frg_id { + 0 => self.syscon.fcclksel0.write(sel_val), + 1 => self.syscon.fcclksel1.write(sel_val), + 2 => self.syscon.fcclksel2.write(sel_val), + 3 => self.syscon.fcclksel3.write(sel_val), + 4 => self.syscon.fcclksel4.write(sel_val), + 5 => self.syscon.fcclksel5.write(sel_val), + 6 => self.syscon.fcclksel6.write(sel_val), + 7 => self.syscon.fcclksel7.write(sel_val), + _ => {} + } + } + + pub fn get_frg_clock_frequency(&self, source: FrgClockSource) -> u32 { + match source { + FrgClockSource::Fro12Mhz => 12_000_000, + FrgClockSource::Fro96Mhz => 96_000_000, + FrgClockSource::Fro1Mhz => 1_000_000, + FrgClockSource::Osc32Khz => 32_768, + FrgClockSource::MainClock => 12_000_000, //not definitive, should check mainclksel + FrgClockSource::SystemPll => 0, + FrgClockSource::Mclk => 0, + FrgClockSource::NoClock => 0, + } + } + + pub fn setup_uart_clock(&self, flexcomm_id: u32, frg_source: FrgClockSource) { + // Enabling the bus clock for the peripheral + match flexcomm_id { + 0 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC0::SET), + 1 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC1::SET), + 2 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC2::SET), + 3 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC3::SET), + 4 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC4::SET), + 5 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC5::SET), + 6 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC6::SET), + 7 => self + .syscon + .ahbclkctrl1 + .modify(syscon::AHBCLKCTRL1::FC7::SET), + _ => return, + } + + // Setting the clock source for the Fractional Rate Divider + self.set_frg_clock_source(flexcomm_id, frg_source); + } +} diff --git a/chips/lpc55s6x/src/ctimer0.rs b/chips/lpc55s6x/src/ctimer0.rs new file mode 100644 index 0000000000..4b22714a76 --- /dev/null +++ b/chips/lpc55s6x/src/ctimer0.rs @@ -0,0 +1,483 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use cortexm33::support::with_interrupts_disabled; +use kernel::hil; +use kernel::hil::time::{Alarm, Ticks, Ticks32, Time}; +use kernel::utilities::cells::{OptionalCell, VolatileCell}; +use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; +use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite}; +use kernel::utilities::StaticRef; + +use crate::interrupts::CTIMER0; + +register_structs! { + /// Standard counter/timers (CTIMER0 to 4) + Ctimer0Registers { + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be rea + (0x000 => ir: ReadWrite), + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + (0x004 => tcr: ReadWrite), + /// Timer Counter + (0x008 => tc: ReadWrite), + /// Prescale Register + (0x00C => pr: ReadWrite), + /// Prescale Counter + (0x010 => pc: ReadWrite), + /// Match Control Register + (0x014 => mcr: ReadWrite), + /// Match Register . MR can be enabled through the MCR to reset the TC, stop both th + (0x018 => mr_0: ReadWrite), + /// Match Register . MR can be enabled through the MCR to reset the TC, stop both th + (0x01C => mr_1: ReadWrite), + /// Match Register . MR can be enabled through the MCR to reset the TC, stop both th + (0x020 => mr_2: ReadWrite), + /// Match Register . MR can be enabled through the MCR to reset the TC, stop both th + (0x024 => mr_3: ReadWrite), + /// Capture Control Register. The CCR controls which edges of the capture inputs are + (0x028 => ccr: ReadWrite), + /// Capture Register . CR is loaded with the value of TC when there is an event on t + (0x02C => cr_0: ReadOnly), + /// Capture Register . CR is loaded with the value of TC when there is an event on t + (0x030 => cr_1: ReadOnly), + /// Capture Register . CR is loaded with the value of TC when there is an event on t + (0x034 => cr_2: ReadOnly), + /// Capture Register . CR is loaded with the value of TC when there is an event on t + (0x038 => cr_3: ReadOnly), + /// External Match Register. The EMR controls the match function and the external ma + (0x03C => emr: ReadWrite), + (0x040 => _reserved0), + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + (0x070 => ctcr: ReadWrite), + /// PWM Control Register. This register enables PWM mode for the external match pins + (0x074 => pwmc: ReadWrite), + /// Match Shadow Register + (0x078 => msr_0: ReadWrite), + /// Match Shadow Register + (0x07C => msr_1: ReadWrite), + /// Match Shadow Register + (0x080 => msr_2: ReadWrite), + /// Match Shadow Register + (0x084 => msr_3: ReadWrite), + (0x088 => @END), + } +} +register_bitfields![u32, +IR [ + MR0INT OFFSET(0) NUMBITS(1) [], + MR1INT OFFSET(1) NUMBITS(1) [], + MR2INT OFFSET(2) NUMBITS(1) [], + MR3INT OFFSET(3) NUMBITS(1) [], + CR0INT OFFSET(4) NUMBITS(1) [], + CR1INT OFFSET(5) NUMBITS(1) [], + CR2INT OFFSET(6) NUMBITS(1) [], + CR3INT OFFSET(7) NUMBITS(1) [], +], +TCR [ + /// Counter enable. + CEN OFFSET(0) NUMBITS(1) [ + /// Disabled.The counters are disabled. + DisabledTheCountersAreDisabled = 0, + /// Enabled. The Timer Counter and Prescale Counter are enabled. + EnabledTheTimerCounterAndPrescaleCounterAreEnabled = 1 + ], + /// Counter reset. + CRST OFFSET(1) NUMBITS(1) [ + /// Disabled. Do nothing. + DisabledDoNothing = 0, + /// Enabled. The Timer Counter and the Prescale Counter are synchronously reset on t + ENABLED = 1 + ] +], +TC [ + /// Timer counter value. + TCVAL OFFSET(0) NUMBITS(32) [] +], +PR [ + /// Prescale counter value. + PRVAL OFFSET(0) NUMBITS(32) [] +], +PC [ + /// Prescale counter value. + PCVAL OFFSET(0) NUMBITS(32) [] +], +MCR [ + /// Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC + MR0I OFFSET(0) NUMBITS(1) [], + /// Reset on MR0: the TC will be reset if MR0 matches it. + MR0R OFFSET(1) NUMBITS(1) [], + /// Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 ma + MR0S OFFSET(2) NUMBITS(1) [], + /// Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC + MR1I OFFSET(3) NUMBITS(1) [], + /// Reset on MR1: the TC will be reset if MR1 matches it. + MR1R OFFSET(4) NUMBITS(1) [], + /// Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 ma + MR1S OFFSET(5) NUMBITS(1) [], + /// Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC + MR2I OFFSET(6) NUMBITS(1) [], + /// Reset on MR2: the TC will be reset if MR2 matches it. + MR2R OFFSET(7) NUMBITS(1) [], + /// Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 ma + MR2S OFFSET(8) NUMBITS(1) [], + /// Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC + MR3I OFFSET(9) NUMBITS(1) [], + /// Reset on MR3: the TC will be reset if MR3 matches it. + MR3R OFFSET(10) NUMBITS(1) [], + /// Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 ma + MR3S OFFSET(11) NUMBITS(1) [], + /// Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset + MR0RL OFFSET(24) NUMBITS(1) [], + /// Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset + MR1RL OFFSET(25) NUMBITS(1) [], + /// Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset + MR2RL OFFSET(26) NUMBITS(1) [], + /// Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset + MR3RL OFFSET(27) NUMBITS(1) [] +], +CCR [ + /// Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded + CAP0RE OFFSET(0) NUMBITS(1) [], + /// Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loade + CAP0FE OFFSET(1) NUMBITS(1) [], + /// Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt + CAP0I OFFSET(2) NUMBITS(1) [], + /// Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded + CAP1RE OFFSET(3) NUMBITS(1) [], + /// Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loade + CAP1FE OFFSET(4) NUMBITS(1) [], + /// Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt + CAP1I OFFSET(5) NUMBITS(1) [], + /// Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded + CAP2RE OFFSET(6) NUMBITS(1) [], + /// Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loade + CAP2FE OFFSET(7) NUMBITS(1) [], + /// Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt + CAP2I OFFSET(8) NUMBITS(1) [], + /// Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded + CAP3RE OFFSET(9) NUMBITS(1) [], + /// Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loade + CAP3FE OFFSET(10) NUMBITS(1) [], + /// Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt + CAP3I OFFSET(11) NUMBITS(1) [] +], +EMR [ + /// External Match 0. This bit reflects the state of output MAT0, whether or not thi + EM0 OFFSET(0) NUMBITS(1) [], + /// External Match 1. This bit reflects the state of output MAT1, whether or not thi + EM1 OFFSET(1) NUMBITS(1) [], + /// External Match 2. This bit reflects the state of output MAT2, whether or not thi + EM2 OFFSET(2) NUMBITS(1) [], + /// External Match 3. This bit reflects the state of output MAT3, whether or not thi + EM3 OFFSET(3) NUMBITS(1) [], + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0 OFFSET(4) NUMBITS(2) [ + /// Do Nothing. + DoNothing = 0, + /// Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW i + ClearClearTheCorrespondingExternalMatchBitOutputTo0MAT0PinIsLOWIfPinnedOut = 1, + /// Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if p + SetSetTheCorrespondingExternalMatchBitOutputTo1MAT0PinIsHIGHIfPinnedOut = 2, + /// Toggle. Toggle the corresponding External Match bit/output. + ToggleToggleTheCorrespondingExternalMatchBitOutput = 3 + ], + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1 OFFSET(6) NUMBITS(2) [ + /// Do Nothing. + DoNothing = 0, + /// Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW i + ClearClearTheCorrespondingExternalMatchBitOutputTo0MAT1PinIsLOWIfPinnedOut = 1, + /// Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if p + SetSetTheCorrespondingExternalMatchBitOutputTo1MAT1PinIsHIGHIfPinnedOut = 2, + /// Toggle. Toggle the corresponding External Match bit/output. + ToggleToggleTheCorrespondingExternalMatchBitOutput = 3 + ], + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2 OFFSET(8) NUMBITS(2) [ + /// Do Nothing. + DoNothing = 0, + /// Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW i + ClearClearTheCorrespondingExternalMatchBitOutputTo0MAT2PinIsLOWIfPinnedOut = 1, + /// Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if p + SetSetTheCorrespondingExternalMatchBitOutputTo1MAT2PinIsHIGHIfPinnedOut = 2, + /// Toggle. Toggle the corresponding External Match bit/output. + ToggleToggleTheCorrespondingExternalMatchBitOutput = 3 + ], + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3 OFFSET(10) NUMBITS(2) [ + /// Do Nothing. + DoNothing = 0, + /// Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW i + ClearClearTheCorrespondingExternalMatchBitOutputTo0MAT3PinIsLOWIfPinnedOut = 1, + /// Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if p + SetSetTheCorrespondingExternalMatchBitOutputTo1MAT3PinIsHIGHIfPinnedOut = 2, + /// Toggle. Toggle the corresponding External Match bit/output. + ToggleToggleTheCorrespondingExternalMatchBitOutput = 3 + ] +], +CTCR [ + /// Counter/Timer Mode This field selects which rising APB bus clock edges can incre + CTMODE OFFSET(0) NUMBITS(2) [ + /// Timer Mode. Incremented every rising APB bus clock edge. + TimerModeIncrementedEveryRisingAPBBusClockEdge = 0, + /// Counter Mode rising edge. TC is incremented on rising edges on the CAP input sel + CounterModeRisingEdgeTCIsIncrementedOnRisingEdgesOnTheCAPInputSelectedByBits32 = 1, + /// Counter Mode falling edge. TC is incremented on falling edges on the CAP input s + COUNTER_FALLING_EDGE = 2, + /// Counter Mode dual edge. TC is incremented on both edges on the CAP input selecte + CounterModeDualEdgeTCIsIncrementedOnBothEdgesOnTheCAPInputSelectedByBits32 = 3 + ], + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + CINSEL OFFSET(2) NUMBITS(2) [ + /// Channel 0. CAPn.0 for CTIMERn + Channel0CAPn0ForCTIMERn = 0, + /// Channel 1. CAPn.1 for CTIMERn + Channel1CAPn1ForCTIMERn = 1, + /// Channel 2. CAPn.2 for CTIMERn + Channel2CAPn2ForCTIMERn = 2, + /// Channel 3. CAPn.3 for CTIMERn + Channel3CAPn3ForCTIMERn = 3 + ], + /// Setting this bit to 1 enables clearing of the timer and the prescaler when the c + ENCC OFFSET(4) NUMBITS(1) [], + /// Edge select. When bit 4 is 1, these bits select which capture input edge will ca + SELCC OFFSET(5) NUMBITS(3) [ + /// Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the + CHANNEL_0_RISING = 0, + /// Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears t + CHANNEL_0_FALLING = 1, + /// Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the + CHANNEL_1_RISING = 2, + /// Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears t + CHANNEL_1_FALLING = 3, + /// Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the + CHANNEL_2_RISING = 4, + /// Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears t + CHANNEL_2_FALLING = 5 + ] +], +PWMC [ + /// PWM mode enable for channel0. + PWMEN0 OFFSET(0) NUMBITS(1) [ + /// Match. CTIMERn_MAT0 is controlled by EM0. + MatchCTIMERn_MAT0IsControlledByEM0 = 0, + /// PWM. PWM mode is enabled for CTIMERn_MAT0. + PWMPWMModeIsEnabledForCTIMERn_MAT0 = 1 + ], + /// PWM mode enable for channel1. + PWMEN1 OFFSET(1) NUMBITS(1) [ + /// Match. CTIMERn_MAT01 is controlled by EM1. + MatchCTIMERn_MAT01IsControlledByEM1 = 0, + /// PWM. PWM mode is enabled for CTIMERn_MAT1. + PWMPWMModeIsEnabledForCTIMERn_MAT1 = 1 + ], + /// PWM mode enable for channel2. + PWMEN2 OFFSET(2) NUMBITS(1) [ + /// Match. CTIMERn_MAT2 is controlled by EM2. + MatchCTIMERn_MAT2IsControlledByEM2 = 0, + /// PWM. PWM mode is enabled for CTIMERn_MAT2. + PWMPWMModeIsEnabledForCTIMERn_MAT2 = 1 + ], + /// PWM mode enable for channel3. Note: It is recommended to use match channel 3 to + PWMEN3 OFFSET(3) NUMBITS(1) [ + /// Match. CTIMERn_MAT3 is controlled by EM3. + MatchCTIMERn_MAT3IsControlledByEM3 = 0, + /// PWM. PWM mode is enabled for CT132Bn_MAT3. + PWMPWMModeIsEnabledForCT132Bn_MAT3 = 1 + ] +], +MR0 [ + /// Timer counter match value. + MATCH OFFSET(0) NUMBITS(32) [] +], +MR1 [ + /// Timer counter match value. + MATCH OFFSET(0) NUMBITS(32) [] +], +MR2 [ + /// Timer counter match value. + MATCH OFFSET(0) NUMBITS(32) [] +], +MR3 [ + /// Timer counter match value. + MATCH OFFSET(0) NUMBITS(32) [] +], +CR0 [ + /// Timer counter capture value. + CAP OFFSET(0) NUMBITS(32) [] +], +CR1 [ + /// Timer counter capture value. + CAP OFFSET(0) NUMBITS(32) [] +], +CR2 [ + /// Timer counter capture value. + CAP OFFSET(0) NUMBITS(32) [] +], +CR3 [ + /// Timer counter capture value. + CAP OFFSET(0) NUMBITS(32) [] +], +MSR0 [ + /// Timer counter match shadow value. + SHADOW OFFSET(0) NUMBITS(32) [] +], +MSR1 [ + /// Timer counter match shadow value. + SHADOW OFFSET(0) NUMBITS(32) [] +], +MSR2 [ + /// Timer counter match shadow value. + SHADOW OFFSET(0) NUMBITS(32) [] +], +MSR3 [ + /// Timer counter match shadow value. + SHADOW OFFSET(0) NUMBITS(32) [] +] +]; + +const CTIMER0_BASE: StaticRef = + unsafe { StaticRef::new(0x50008000 as *const Ctimer0Registers) }; + +pub struct LPCTimer<'a> { + registers: StaticRef, + client: OptionalCell<&'a dyn hil::time::AlarmClient>, + armed: VolatileCell, +} + +impl<'a> LPCTimer<'a> { + pub const fn new() -> LPCTimer<'a> { + LPCTimer { + registers: CTIMER0_BASE, + client: OptionalCell::empty(), + armed: VolatileCell::new(false), + } + } + + pub fn init(&self, pclk_hz: u32) { + let pr = pclk_hz / 1_000_000 - 1; + + self.registers.tcr.modify(TCR::CRST::SET); + self.registers.tcr.modify(TCR::CRST::CLEAR); + + self.registers.tcr.set(0x1); + + self.registers.ctcr.set(0); + + self.registers.pr.set(pr); + + self.registers.pc.set(0); + + self.registers.tcr.modify(TCR::CEN::SET); + + self.registers.mr_0.set(250_000); + + self.registers + .mcr + .modify(MCR::MR0R::CLEAR + MCR::MR0S::CLEAR + MCR::MR0I::CLEAR); + + self.registers.ir.modify(IR::MR0INT::SET); + } + + fn enable_interrupt(&self) { + self.registers.mcr.modify(MCR::MR0I::SET); + } + + fn disable_interrupt(&self) { + self.registers.mcr.modify(MCR::MR0I::CLEAR); + } + + fn enable_timer_interrupt(&self) { + unsafe { + with_interrupts_disabled(|| { + let n = cortexm33::nvic::Nvic::new(CTIMER0); + n.enable(); + }) + } + } + + #[allow(dead_code)] + fn disable_timer_interrupt(&self) { + unsafe { + cortexm33::nvic::Nvic::new(CTIMER0).disable(); + } + } + + pub fn handle_interrupt(&self) { + self.registers.ir.modify(IR::MR0INT::SET); + + self.armed.set(false); + + self.client.map(|client| client.alarm()); + } + + pub fn get_pr(&self) -> u32 { + self.registers.pr.get() + } +} + +impl Time for LPCTimer<'_> { + type Frequency = hil::time::Freq1MHz; + type Ticks = Ticks32; + + fn now(&self) -> Self::Ticks { + self.registers.tcr.set(0x1); + + Self::Ticks::from(self.registers.tc.get()) + } +} + +impl<'a> Alarm<'a> for LPCTimer<'a> { + fn set_alarm_client(&self, client: &'a dyn hil::time::AlarmClient) { + self.client.set(client) + } + + fn set_alarm(&self, reference: Self::Ticks, dt: Self::Ticks) { + let mut expire = reference.wrapping_add(dt); + let now = self.now(); + + if !now.within_range(reference, expire) { + expire = now; + } + + let min = self.minimum_dt(); + if expire.wrapping_sub(now) < min { + expire = now.wrapping_add(min); + } + + self.registers.mr_0.set(expire.into_u32()); + + self.registers.ir.modify(IR::MR0INT::SET); + + self.enable_interrupt(); + self.enable_timer_interrupt(); + + self.armed.set(true); + } + + fn get_alarm(&self) -> Self::Ticks { + Self::Ticks::from(self.registers.mr_0.get()) + } + + fn disarm(&self) -> Result<(), kernel::ErrorCode> { + self.disable_interrupt(); + self.armed.set(false); + + unsafe { + with_interrupts_disabled(|| { + cortexm33::nvic::Nvic::new(CTIMER0).clear_pending(); + }); + } + + Ok(()) + } + + fn is_armed(&self) -> bool { + self.armed.get() + } + + fn minimum_dt(&self) -> Self::Ticks { + Self::Ticks::from(50) + } +} diff --git a/chips/lpc55s6x/src/gpio.rs b/chips/lpc55s6x/src/gpio.rs new file mode 100644 index 0000000000..0af7c65520 --- /dev/null +++ b/chips/lpc55s6x/src/gpio.rs @@ -0,0 +1,578 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::hil::gpio; +use kernel::utilities::cells::OptionalCell; +use kernel::utilities::registers::interfaces::{Readable, Writeable}; +use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite, WriteOnly}; +use kernel::utilities::StaticRef; + +register_structs! { + pub GpioRegisters { + (0x0000 => _reserved0: [u8; 0x2000]), + (0x2000 => dir_0: ReadWrite), + (0x2004 => dir_1: ReadWrite), + (0x2008 => _reserved1: [u8; 0x78]), + (0x2080 => mask_0: ReadWrite), + (0x2084 => mask_1: ReadWrite), + (0x2088 => _reserved2: [u8; 0x78]), + (0x2100 => pin_0: ReadWrite), + (0x2104 => pin_1: ReadWrite), + (0x2108 => _reserved3: [u8; 0x78]), + (0x2180 => mpin_0: ReadWrite), + (0x2184 => mpin_1: ReadWrite), + (0x2188 => _reserved4: [u8; 0x78]), + (0x2200 => set_0: WriteOnly), + (0x2204 => set_1: WriteOnly), + (0x2208 => _reserved5: [u8; 0x78]), + (0x2280 => clr_0: WriteOnly), + (0x2284 => clr_1: WriteOnly), + (0x2288 => _reserved6: [u8; 0x78]), + (0x2300 => not_0: WriteOnly), + (0x2304 => not_1: WriteOnly), + (0x2308 => _reserved7: [u8; 0x78]), + (0x2380 => dirset_0: WriteOnly), + (0x2384 => dirset_1: WriteOnly), + (0x2388 => _reserved8: [u8; 0x78]), + (0x2400 => dirclr_0: WriteOnly), + (0x2404 => dirclr_1: WriteOnly), + (0x2408 => _reserved9: [u8; 0x78]), + (0x2480 => dirnot_0: WriteOnly), + (0x2484 => dirnot_1: WriteOnly), + (0x2488 => @END), + } +} + +register_bitfields![u32, + DIR [ DIRP OFFSET(0) NUMBITS(32) [] ], MASK [ MASKP OFFSET(0) NUMBITS(32) [] ], + PIN [ PORT OFFSET(0) NUMBITS(32) [] ], MPIN [ MPORTP OFFSET(0) NUMBITS(32) [] ], + SET [ SETP OFFSET(0) NUMBITS(32) [] ], CLR [ CLRP OFFSET(0) NUMBITS(32) [] ], + NOT [ NOTP OFFSET(0) NUMBITS(32) [] ], DIRSET [ DIRSETP OFFSET(0) NUMBITS(32) [] ], + DIRCLR [ DIRCLRP OFFSET(0) NUMBITS(32) [] ], DIRNOT [ DIRNOTP OFFSET(0) NUMBITS(32) [] ] +]; + +pub(crate) const GPIO_BASE: StaticRef = + unsafe { StaticRef::new(0x5008_C000 as *const GpioRegisters) }; + +#[derive(Clone, Copy, Debug, PartialEq)] +#[allow(non_camel_case_types)] +pub enum LPCPin { + P0_0 = 0, + P0_1 = 1, + P0_2 = 2, + P0_3 = 3, + P0_4 = 4, + P0_5 = 5, + P0_6 = 6, + P0_7 = 7, + P0_8 = 8, + P0_9 = 9, + P0_10 = 10, + P0_11 = 11, + P0_12 = 12, + P0_13 = 13, + P0_14 = 14, + P0_15 = 15, + P0_16 = 16, + P0_17 = 17, + P0_18 = 18, + P0_19 = 19, + P0_20 = 20, + P0_21 = 21, + P0_22 = 22, + P0_23 = 23, + P0_24 = 24, + P0_25 = 25, + P0_26 = 26, + P0_27 = 27, + P0_28 = 28, + P0_29 = 29, + P0_30 = 30, + P0_31 = 31, + P1_0 = 32, + P1_1 = 33, + P1_2 = 34, + P1_3 = 35, + P1_4 = 36, + P1_5 = 37, + P1_6 = 38, + P1_7 = 39, + P1_8 = 40, + P1_9 = 41, + P1_10 = 42, + P1_11 = 43, + P1_12 = 44, + P1_13 = 45, + P1_14 = 46, + P1_15 = 47, + P1_16 = 48, + P1_17 = 49, + P1_18 = 50, + P1_19 = 51, + P1_20 = 52, + P1_21 = 53, + P1_22 = 54, + P1_23 = 55, + P1_24 = 56, + P1_25 = 57, + P1_26 = 58, + P1_27 = 59, + P1_28 = 60, + P1_29 = 61, + P1_30 = 62, + P1_31 = 63, +} + +pub struct Pins<'a> { + pub pins: [Option>; 64], + pub inputmux: Inputmux, + pub iocon: Iocon, + pub pint: Pint<'a>, +} + +impl<'a> Pins<'a> { + pub const fn new() -> Self { + let inputmux = Inputmux::new(); + let iocon = Iocon::new(); + let pint = Pint::new(); + Self { + pins: [ + Some(GpioPin::new(LPCPin::P0_0)), + Some(GpioPin::new(LPCPin::P0_1)), + Some(GpioPin::new(LPCPin::P0_2)), + Some(GpioPin::new(LPCPin::P0_3)), + Some(GpioPin::new(LPCPin::P0_4)), + Some(GpioPin::new(LPCPin::P0_5)), + Some(GpioPin::new(LPCPin::P0_6)), + Some(GpioPin::new(LPCPin::P0_7)), + Some(GpioPin::new(LPCPin::P0_8)), + Some(GpioPin::new(LPCPin::P0_9)), + Some(GpioPin::new(LPCPin::P0_10)), + Some(GpioPin::new(LPCPin::P0_11)), + Some(GpioPin::new(LPCPin::P0_12)), + Some(GpioPin::new(LPCPin::P0_13)), + Some(GpioPin::new(LPCPin::P0_14)), + Some(GpioPin::new(LPCPin::P0_15)), + Some(GpioPin::new(LPCPin::P0_16)), + Some(GpioPin::new(LPCPin::P0_17)), + Some(GpioPin::new(LPCPin::P0_18)), + Some(GpioPin::new(LPCPin::P0_19)), + Some(GpioPin::new(LPCPin::P0_20)), + Some(GpioPin::new(LPCPin::P0_21)), + Some(GpioPin::new(LPCPin::P0_22)), + Some(GpioPin::new(LPCPin::P0_23)), + Some(GpioPin::new(LPCPin::P0_24)), + Some(GpioPin::new(LPCPin::P0_25)), + Some(GpioPin::new(LPCPin::P0_26)), + Some(GpioPin::new(LPCPin::P0_27)), + Some(GpioPin::new(LPCPin::P0_28)), + Some(GpioPin::new(LPCPin::P0_29)), + Some(GpioPin::new(LPCPin::P0_30)), + Some(GpioPin::new(LPCPin::P0_31)), + Some(GpioPin::new(LPCPin::P1_0)), + Some(GpioPin::new(LPCPin::P1_1)), + Some(GpioPin::new(LPCPin::P1_2)), + Some(GpioPin::new(LPCPin::P1_3)), + Some(GpioPin::new(LPCPin::P1_4)), + Some(GpioPin::new(LPCPin::P1_5)), + Some(GpioPin::new(LPCPin::P1_6)), + Some(GpioPin::new(LPCPin::P1_7)), + Some(GpioPin::new(LPCPin::P1_8)), + Some(GpioPin::new(LPCPin::P1_9)), + Some(GpioPin::new(LPCPin::P1_10)), + Some(GpioPin::new(LPCPin::P1_11)), + Some(GpioPin::new(LPCPin::P1_12)), + Some(GpioPin::new(LPCPin::P1_13)), + Some(GpioPin::new(LPCPin::P1_14)), + Some(GpioPin::new(LPCPin::P1_15)), + Some(GpioPin::new(LPCPin::P1_16)), + Some(GpioPin::new(LPCPin::P1_17)), + Some(GpioPin::new(LPCPin::P1_18)), + Some(GpioPin::new(LPCPin::P1_19)), + Some(GpioPin::new(LPCPin::P1_20)), + Some(GpioPin::new(LPCPin::P1_21)), + Some(GpioPin::new(LPCPin::P1_22)), + Some(GpioPin::new(LPCPin::P1_23)), + Some(GpioPin::new(LPCPin::P1_24)), + Some(GpioPin::new(LPCPin::P1_25)), + Some(GpioPin::new(LPCPin::P1_26)), + Some(GpioPin::new(LPCPin::P1_27)), + Some(GpioPin::new(LPCPin::P1_28)), + Some(GpioPin::new(LPCPin::P1_29)), + Some(GpioPin::new(LPCPin::P1_30)), + Some(GpioPin::new(LPCPin::P1_31)), + ], + inputmux, + iocon, + pint, + } + } + pub fn get_pin(&self, searched_pin: LPCPin) -> &'a GpioPin { + self.pins[searched_pin as usize].as_ref().unwrap() + } + + pub fn handle_interrupt(&self) { + self.pint.handle_interrupt(); + + for pin in self.pins.iter() { + if let Some(gpio_pin) = pin { + gpio_pin.handle_interrupt(); + } + } + } + + pub fn set_inputmux(&'a self) { + for pin in self.pins.iter() { + if let Some(gpio_pin) = pin { + gpio_pin.set_inputmux(&self.inputmux); + } + } + } + + pub fn set_iocon(&'a self) { + for pin in self.pins.iter() { + if let Some(gpio_pin) = pin { + gpio_pin.set_iocon(&self.iocon); + } + } + } + + pub fn set_pint(&'a self) { + for pin in self.pins.iter() { + if let Some(gpio_pin) = pin { + gpio_pin.set_pint(&self.pint); + } + } + } + + pub fn init(&'a self) { + self.set_inputmux(); + self.set_iocon(); + self.set_pint(); + } +} + +pub struct GpioPin<'a> { + registers: StaticRef, + port: u8, + pin: u8, + // pint_channel: OptionalCell, + client: OptionalCell<&'a dyn gpio::Client>, + inputmux: OptionalCell<&'a Inputmux>, + iocon: OptionalCell<&'a Iocon>, + pint: OptionalCell<&'a Pint<'a>>, +} + +pub use kernel::hil::gpio::{Configure, Input, Interrupt, Output, Pin}; + +use crate::inputmux::Inputmux; +use crate::iocon::Iocon; +use crate::pint::{Edge, Pint}; + +impl<'a> GpioPin<'a> { + pub const fn new(pin_name: LPCPin) -> Self { + let pin_num = pin_name as u8; + Self { + registers: GPIO_BASE, + port: pin_num / 32, + pin: pin_num % 32, + // pint_channel: OptionalCell::empty(), + client: OptionalCell::empty(), + inputmux: OptionalCell::empty(), + iocon: OptionalCell::empty(), + pint: OptionalCell::empty(), + } + } + + fn pin_mask(&self) -> u32 { + 1 << self.pin + } + + fn is_output(&self) -> bool { + match self.port { + 0 => (self.registers.dir_0.get() & self.pin_mask()) != 0, + 1 => (self.registers.dir_1.get() & self.pin_mask()) != 0, + _ => false, + } + } + + pub fn get_pin_num(&self) -> usize { + (self.port as usize * 32) + self.pin as usize + } + + pub fn handle_interrupt(&self) { + self.pint.map(|pint| { + pint.handle_interrupt(); + }); + } + + pub fn set_inputmux(&self, inputmux: &'a Inputmux) { + self.inputmux.set(inputmux); + } + pub fn set_iocon(&self, iocon: &'a Iocon) { + self.iocon.set(iocon); + } + pub fn set_pint(&self, pint: &'a Pint<'a>) { + self.pint.set(pint); + } +} + +impl gpio::Output for GpioPin<'_> { + fn set(&self) { + match self.port { + 0 => self.registers.set_0.write(SET::SETP.val(self.pin_mask())), + 1 => self.registers.set_1.write(SET::SETP.val(self.pin_mask())), + _ => {} + } + } + + fn clear(&self) { + match self.port { + 0 => self.registers.clr_0.write(CLR::CLRP.val(self.pin_mask())), + 1 => self.registers.clr_1.write(CLR::CLRP.val(self.pin_mask())), + _ => {} + } + } + + fn toggle(&self) -> bool { + match self.port { + 0 => self.registers.not_0.write(NOT::NOTP.val(self.pin_mask())), + 1 => self.registers.not_1.write(NOT::NOTP.val(self.pin_mask())), + _ => {} + } + self.read() + } +} + +impl gpio::Input for GpioPin<'_> { + fn read(&self) -> bool { + match self.port { + 0 => self.registers.pin_0.get() & self.pin_mask() != 0, + 1 => self.registers.pin_1.get() & self.pin_mask() != 0, + _ => false, + } + } +} + +impl gpio::Configure for GpioPin<'_> { + fn make_output(&self) -> gpio::Configuration { + match self.port { + 0 => self + .registers + .dirset_0 + .write(DIRSET::DIRSETP.val(self.pin_mask())), + 1 => self + .registers + .dirset_1 + .write(DIRSET::DIRSETP.val(self.pin_mask())), + _ => {} + } + gpio::Configuration::Output + } + + fn make_input(&self) -> gpio::Configuration { + match self.port { + 0 => self + .registers + .dirclr_0 + .write(DIRCLR::DIRCLRP.val(self.pin_mask())), + 1 => self + .registers + .dirclr_1 + .write(DIRCLR::DIRCLRP.val(self.pin_mask())), + _ => {} + } + gpio::Configuration::Input + } + + fn configuration(&self) -> gpio::Configuration { + if self.is_output() { + gpio::Configuration::Output + } else { + gpio::Configuration::Input + } + } + + fn set_floating_state(&self, state: kernel::hil::gpio::FloatingState) { + let pins = [ + LPCPin::P0_0, + LPCPin::P0_1, + LPCPin::P0_2, + LPCPin::P0_3, + LPCPin::P0_4, + LPCPin::P0_5, + LPCPin::P0_6, + LPCPin::P0_7, + LPCPin::P0_8, + LPCPin::P0_9, + LPCPin::P0_10, + LPCPin::P0_11, + LPCPin::P0_12, + LPCPin::P0_13, + LPCPin::P0_14, + LPCPin::P0_15, + LPCPin::P0_16, + LPCPin::P0_17, + LPCPin::P0_18, + LPCPin::P0_19, + LPCPin::P0_20, + LPCPin::P0_21, + LPCPin::P0_22, + LPCPin::P0_23, + LPCPin::P0_24, + LPCPin::P0_25, + LPCPin::P0_26, + LPCPin::P0_27, + LPCPin::P0_28, + LPCPin::P0_29, + LPCPin::P0_30, + LPCPin::P0_31, + LPCPin::P1_0, + LPCPin::P1_1, + LPCPin::P1_2, + LPCPin::P1_3, + LPCPin::P1_4, + LPCPin::P1_5, + LPCPin::P1_6, + LPCPin::P1_7, + LPCPin::P1_8, + LPCPin::P1_9, + LPCPin::P1_10, + LPCPin::P1_11, + LPCPin::P1_12, + LPCPin::P1_13, + LPCPin::P1_14, + LPCPin::P1_15, + LPCPin::P1_16, + LPCPin::P1_17, + LPCPin::P1_18, + LPCPin::P1_19, + LPCPin::P1_20, + LPCPin::P1_21, + LPCPin::P1_22, + LPCPin::P1_23, + LPCPin::P1_24, + LPCPin::P1_25, + LPCPin::P1_26, + LPCPin::P1_27, + LPCPin::P1_28, + LPCPin::P1_29, + LPCPin::P1_30, + LPCPin::P1_31, + ]; + + for pin in pins.iter() { + match state { + gpio::FloatingState::PullNone => { + self.iocon.map(|iocon| { + iocon.set_pull_none(*pin); + }); + } + gpio::FloatingState::PullUp => { + self.iocon.map(|iocon| { + iocon.set_pull_up(*pin); + }); + } + gpio::FloatingState::PullDown => { + self.iocon.map(|iocon| { + iocon.set_pull_down(*pin); + }); + } + } + } + } + fn floating_state(&self) -> gpio::FloatingState { + gpio::FloatingState::PullNone + } + fn disable_input(&self) -> gpio::Configuration { + self.make_output() + } + fn disable_output(&self) -> gpio::Configuration { + self.make_input() + } + fn deactivate_to_low_power(&self) { + let _state = gpio::FloatingState::PullNone; + self.make_input(); + } +} + +impl<'a> gpio::Interrupt<'a> for GpioPin<'a> { + fn set_client(&self, client: &'a dyn gpio::Client) { + self.client.set(client); + self.pint.map(|pint| { + pint.set_client(0, client); + }); + } + + fn enable_interrupts(&self, mode: gpio::InterruptEdge) { + match mode { + gpio::InterruptEdge::RisingEdge => { + self.pint.map(|pint| { + pint.configure_interrupt(0, Edge::Rising); + }); + } + gpio::InterruptEdge::FallingEdge => { + self.pint.map(|pint| { + pint.configure_interrupt(0, Edge::Falling); + }); + } + gpio::InterruptEdge::EitherEdge => { + self.pint.map(|pint| { + pint.configure_interrupt(0, Edge::Both); + }); + } + } + } + + fn disable_interrupts(&self) { + self.pint.map(|pint| { + pint.disable_interrupt(0); + }); + } + + fn is_pending(&self) -> bool { + todo!() + } +} + +// impl<'a> gpio::Interrupt<'a> for GpioPin<'a> { +// fn set_client(&self, client: &'a dyn gpio::Client) { +// self.client.set(client) +// } + +// // fn enable_interrupts(&self, mode: gpio::InterruptEdge) { +// // if self.pint_channel.is_none() { +// // if let Some(channel) = PINT.find_and_take_channel() { +// // self.pint_channel.set(channel); +// // PINT.select_pin(self.get_pin_num(), channel); +// // } +// // } + +// // self.pint_channel.map(|channel|{ +// // self.client.map(|client| PINT.set_client(channel, client)); + +// // let edge = match mode { +// // gpio::InterruptEdge::RisingEdge => Edge::Rising, +// // gpio::InterruptEdge::FallingEdge => Edge:: Falling, +// // gpio::InterruptEdge::EitherEdge => Edge::Both, +// // }; +// // PINT.configure_interrupt(channel.into(), edge); +// // }); +// // } + +// // fn is_interrupt_enabled(&self) -> bool { +// // self.pint_channel.is_some() +// // } + +// // fn disable_interrupts(&self) { +// // self.pint_channel.map(|channel| { +// // PINT.disable_and_free_channel(channel); +// // }); +// // self.pint_channel.clear(); +// // } + +// fn is_pending(&self) -> bool { +// false +// } +// } diff --git a/chips/lpc55s6x/src/inputmux.rs b/chips/lpc55s6x/src/inputmux.rs new file mode 100644 index 0000000000..e754cc9fd2 --- /dev/null +++ b/chips/lpc55s6x/src/inputmux.rs @@ -0,0 +1,263 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::utilities::registers::interfaces::ReadWriteable; +use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite, WriteOnly}; +use kernel::utilities::StaticRef; + +register_structs! { + /// Input multiplexing (INPUT MUX) + pub InputmuxRegisters { + /// Input mux register for SCT0 input + (0x000 => sct0_inmux_0: ReadWrite), + /// Input mux register for SCT0 input + (0x004 => sct0_inmux_1: ReadWrite), + /// Input mux register for SCT0 input + (0x008 => sct0_inmux_2: ReadWrite), + /// Input mux register for SCT0 input + (0x00C => sct0_inmux_3: ReadWrite), + /// Input mux register for SCT0 input + (0x010 => sct0_inmux_4: ReadWrite), + /// Input mux register for SCT0 input + (0x014 => sct0_inmux_5: ReadWrite), + /// Input mux register for SCT0 input + (0x018 => sct0_inmux_6: ReadWrite), + (0x01C => _reserved0), + /// Capture select registers for TIMER0 inputs + (0x020 => timer0captsel_0: ReadWrite), + /// Capture select registers for TIMER0 inputs + (0x024 => timer0captsel_1: ReadWrite), + /// Capture select registers for TIMER0 inputs + (0x028 => timer0captsel_2: ReadWrite), + /// Capture select registers for TIMER0 inputs + (0x02C => timer0captsel_3: ReadWrite), + (0x030 => _reserved1), + /// Capture select registers for TIMER1 inputs + (0x040 => timer1captsel_0: ReadWrite), + /// Capture select registers for TIMER1 inputs + (0x044 => timer1captsel_1: ReadWrite), + /// Capture select registers for TIMER1 inputs + (0x048 => timer1captsel_2: ReadWrite), + /// Capture select registers for TIMER1 inputs + (0x04C => timer1captsel_3: ReadWrite), + (0x050 => _reserved2), + /// Capture select registers for TIMER2 inputs + (0x060 => timer2captsel_0: ReadWrite), + /// Capture select registers for TIMER2 inputs + (0x064 => timer2captsel_1: ReadWrite), + /// Capture select registers for TIMER2 inputs + (0x068 => timer2captsel_2: ReadWrite), + /// Capture select registers for TIMER2 inputs + (0x06C => timer2captsel_3: ReadWrite), + (0x070 => _reserved3), + /// Pin interrupt select register + (0x0C0 => pintsel_0: ReadWrite), + /// Pin interrupt select register + (0x0C4 => pintsel_1: ReadWrite), + /// Pin interrupt select register + (0x0C8 => pintsel_2: ReadWrite), + /// Pin interrupt select register + (0x0CC => pintsel_3: ReadWrite), + /// Pin interrupt select register + (0x0D0 => pintsel_4: ReadWrite), + /// Pin interrupt select register + (0x0D4 => pintsel_5: ReadWrite), + /// Pin interrupt select register + (0x0D8 => pintsel_6: ReadWrite), + /// Pin interrupt select register + (0x0DC => pintsel_7: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0E0 => dma0_itrig_inmux_0: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0E4 => dma0_itrig_inmux_1: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0E8 => dma0_itrig_inmux_2: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0EC => dma0_itrig_inmux_3: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0F0 => dma0_itrig_inmux_4: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0F4 => dma0_itrig_inmux_5: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0F8 => dma0_itrig_inmux_6: ReadWrite), + /// Trigger select register for DMA0 channel + (0x0FC => dma0_itrig_inmux_7: ReadWrite), + /// Trigger select register for DMA0 channel + (0x100 => dma0_itrig_inmux_8: ReadWrite), + /// Trigger select register for DMA0 channel + (0x104 => dma0_itrig_inmux_9: ReadWrite), + /// Trigger select register for DMA0 channel + (0x108 => dma0_itrig_inmux_10: ReadWrite), + /// Trigger select register for DMA0 channel + (0x10C => dma0_itrig_inmux_11: ReadWrite), + /// Trigger select register for DMA0 channel + (0x110 => dma0_itrig_inmux_12: ReadWrite), + /// Trigger select register for DMA0 channel + (0x114 => dma0_itrig_inmux_13: ReadWrite), + /// Trigger select register for DMA0 channel + (0x118 => dma0_itrig_inmux_14: ReadWrite), + /// Trigger select register for DMA0 channel + (0x11C => dma0_itrig_inmux_15: ReadWrite), + /// Trigger select register for DMA0 channel + (0x120 => dma0_itrig_inmux_16: ReadWrite), + /// Trigger select register for DMA0 channel + (0x124 => dma0_itrig_inmux_17: ReadWrite), + /// Trigger select register for DMA0 channel + (0x128 => dma0_itrig_inmux_18: ReadWrite), + /// Trigger select register for DMA0 channel + (0x12C => dma0_itrig_inmux_19: ReadWrite), + /// Trigger select register for DMA0 channel + (0x130 => dma0_itrig_inmux_20: ReadWrite), + /// Trigger select register for DMA0 channel + (0x134 => dma0_itrig_inmux_21: ReadWrite), + /// Trigger select register for DMA0 channel + (0x138 => dma0_itrig_inmux_22: ReadWrite), + (0x13C => _reserved4), + /// DMA0 output trigger selection to become DMA0 trigger + (0x160 => dma0_otrig_inmux_0: ReadWrite), + /// DMA0 output trigger selection to become DMA0 trigger + (0x164 => dma0_otrig_inmux_1: ReadWrite), + /// DMA0 output trigger selection to become DMA0 trigger + (0x168 => dma0_otrig_inmux_2: ReadWrite), + /// DMA0 output trigger selection to become DMA0 trigger + (0x16C => dma0_otrig_inmux_3: ReadWrite), + (0x170 => _reserved5), + /// Selection for frequency measurement reference clock + (0x180 => freqmeas_ref: ReadWrite), + /// Selection for frequency measurement target clock + (0x184 => freqmeas_target: ReadWrite), + (0x188 => _reserved6), + /// Capture select registers for TIMER3 inputs + (0x1A0 => timer3captsel_0: ReadWrite), + /// Capture select registers for TIMER3 inputs + (0x1A4 => timer3captsel_1: ReadWrite), + /// Capture select registers for TIMER3 inputs + (0x1A8 => timer3captsel_2: ReadWrite), + /// Capture select registers for TIMER3 inputs + (0x1AC => timer3captsel_3: ReadWrite), + (0x1B0 => _reserved7), + /// Capture select registers for TIMER4 inputs + (0x1C0 => timer4captsel_0: ReadWrite), + /// Capture select registers for TIMER4 inputs + (0x1C4 => timer4captsel_1: ReadWrite), + /// Capture select registers for TIMER4 inputs + (0x1C8 => timer4captsel_2: ReadWrite), + /// Capture select registers for TIMER4 inputs + (0x1CC => timer4captsel_3: ReadWrite), + (0x1D0 => _reserved8), + /// Pin interrupt secure select register + (0x1E0 => pintsecsel_0: ReadWrite), + /// Pin interrupt secure select register + (0x1E4 => pintsecsel_1: ReadWrite), + (0x1E8 => _reserved9), + /// Trigger select register for DMA1 channel + (0x200 => dma1_itrig_inmux_0: ReadWrite), + /// Trigger select register for DMA1 channel + (0x204 => dma1_itrig_inmux_1: ReadWrite), + /// Trigger select register for DMA1 channel + (0x208 => dma1_itrig_inmux_2: ReadWrite), + /// Trigger select register for DMA1 channel + (0x20C => dma1_itrig_inmux_3: ReadWrite), + /// Trigger select register for DMA1 channel + (0x210 => dma1_itrig_inmux_4: ReadWrite), + /// Trigger select register for DMA1 channel + (0x214 => dma1_itrig_inmux_5: ReadWrite), + /// Trigger select register for DMA1 channel + (0x218 => dma1_itrig_inmux_6: ReadWrite), + /// Trigger select register for DMA1 channel + (0x21C => dma1_itrig_inmux_7: ReadWrite), + /// Trigger select register for DMA1 channel + (0x220 => dma1_itrig_inmux_8: ReadWrite), + /// Trigger select register for DMA1 channel + (0x224 => dma1_itrig_inmux_9: ReadWrite), + (0x228 => _reserved10), + /// DMA1 output trigger selection to become DMA1 trigger + (0x240 => dma1_otrig_inmux_0: ReadWrite), + /// DMA1 output trigger selection to become DMA1 trigger + (0x244 => dma1_otrig_inmux_1: ReadWrite), + /// DMA1 output trigger selection to become DMA1 trigger + (0x248 => dma1_otrig_inmux_2: ReadWrite), + /// DMA1 output trigger selection to become DMA1 trigger + (0x24C => dma1_otrig_inmux_3: ReadWrite), + (0x250 => _reserved11), + /// Enable DMA0 requests + (0x740 => dma0_req_ena: ReadWrite), + (0x744 => _reserved12), + /// Set one or several bits in DMA0_REQ_ENA register + (0x748 => dma0_req_ena_set: WriteOnly), + (0x74C => _reserved13), + /// Clear one or several bits in DMA0_REQ_ENA register + (0x750 => dma0_req_ena_clr: WriteOnly), + (0x754 => _reserved14), + /// Enable DMA1 requests + (0x760 => dma1_req_ena: ReadWrite), + (0x764 => _reserved15), + /// Set one or several bits in DMA1_REQ_ENA register + (0x768 => dma1_req_ena_set: WriteOnly), + (0x76C => _reserved16), + /// Clear one or several bits in DMA1_REQ_ENA register + (0x770 => dma1_req_ena_clr: WriteOnly), + (0x774 => _reserved17), + /// Enable DMA0 triggers + (0x780 => dma0_itrig_ena: ReadWrite), + (0x784 => _reserved18), + /// Set one or several bits in DMA0_ITRIG_ENA register + (0x788 => dma0_itrig_ena_set: WriteOnly), + (0x78C => _reserved19), + /// Clear one or several bits in DMA0_ITRIG_ENA register + (0x790 => dma0_itrig_ena_clr: WriteOnly), + (0x794 => _reserved20), + /// Enable DMA1 triggers + (0x7A0 => dma1_itrig_ena: ReadWrite), + (0x7A4 => _reserved21), + /// Set one or several bits in DMA1_ITRIG_ENA register + (0x7A8 => dma1_itrig_ena_set: WriteOnly), + (0x7AC => _reserved22), + /// Clear one or several bits in DMA1_ITRIG_ENA register + (0x7B0 => dma1_itrig_ena_clr: WriteOnly), + (0x7B4 => @END), + } +} +register_bitfields![u32, +PINTSEL [ + /// Pin number select for pin interrupt or pattern match engine input. For PIOx_y: I + INTPIN OFFSET(0) NUMBITS(7) [] +], +]; +const INPUTMUX_BASE: StaticRef = + unsafe { StaticRef::new(0x50006000 as *const InputmuxRegisters) }; + +pub struct Inputmux { + registers: StaticRef, +} + +// Safety: Inputmux only contains a StaticRef, which is safe to share between threads. + +impl Inputmux { + pub const fn new() -> Self { + Inputmux { + registers: INPUTMUX_BASE, + } + } + + pub fn registers(&self) -> &InputmuxRegisters { + &self.registers + } + + pub fn set_pintsel(&self, channel: usize, pin: u8) { + assert!(channel < 8); + let pintsel = match channel { + 0 => &self.registers.pintsel_0, + 1 => &self.registers.pintsel_1, + 2 => &self.registers.pintsel_2, + 3 => &self.registers.pintsel_3, + 4 => &self.registers.pintsel_4, + 5 => &self.registers.pintsel_5, + 6 => &self.registers.pintsel_6, + 7 => &self.registers.pintsel_7, + _ => unreachable!(), + }; + pintsel.modify(PINTSEL::INTPIN.val(pin as u32)); + } +} diff --git a/chips/lpc55s6x/src/interrupts.rs b/chips/lpc55s6x/src/interrupts.rs new file mode 100644 index 0000000000..190a809d28 --- /dev/null +++ b/chips/lpc55s6x/src/interrupts.rs @@ -0,0 +1,54 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +pub const WDT_BOD_FLASH: u32 = 0; +pub const SDMA0: u32 = 1; +pub const GPIO_GLOBALINT0: u32 = 2; +pub const GPIO_GLOBALINT1: u32 = 3; +pub const GPIO_INT0_IRQ0: u32 = 4; +pub const GPIO_INT0_IRQ1: u32 = 5; +pub const GPIO_INT0_IRQ2: u32 = 6; +pub const GPIO_INT0_IRQ3: u32 = 7; +pub const UTICK: u32 = 8; +pub const MRT: u32 = 9; +pub const CTIMER0: u32 = 10; +pub const CTIMER1: u32 = 11; +pub const SCT: u32 = 12; +pub const CTIMER3: u32 = 13; +pub const FLEXCOMM0: u32 = 14; +pub const FLEXCOMM1: u32 = 15; +pub const FLEXCOMM2: u32 = 16; +pub const FLEXCOMM3: u32 = 17; +pub const FLEXCOMM4: u32 = 18; +pub const FLEXCOMM5: u32 = 19; +pub const FLEXCOMM6: u32 = 20; +pub const FLEXCOMM7: u32 = 21; +pub const ADC: u32 = 22; +pub const ACMP: u32 = 24; +pub const USB0_NEEDCLK: u32 = 27; +pub const USB0: u32 = 28; +pub const RTC: u32 = 29; +pub const WAKEUP_IRQN: u32 = 31; +pub const GPIO_INT0_IRQ4: u32 = 32; +pub const GPIO_INT0_IRQ5: u32 = 33; +pub const GPIO_INT0_IRQ6: u32 = 34; +pub const GPIO_INT0_IRQ7: u32 = 35; +pub const CTIMER2: u32 = 36; +pub const CTIMER4: u32 = 37; +pub const OSEVTIMER: u32 = 38; +pub const SDIO: u32 = 42; +pub const USB1_PHY: u32 = 46; +pub const USB1: u32 = 47; +pub const USB1_NEEDCLK: u32 = 48; +pub const HYPERVISOR: u32 = 49; +pub const SGPIO_INT0_IRQ0: u32 = 50; +pub const SGPIO_INT0_IRQ1: u32 = 51; +pub const PLU: u32 = 52; +pub const SEC_VIO: u32 = 53; +pub const HASH: u32 = 54; +pub const CASPER: u32 = 55; +pub const PUF: u32 = 56; +pub const PQ: u32 = 57; +pub const SDMA1: u32 = 58; +pub const HS_SPI: u32 = 56; diff --git a/chips/lpc55s6x/src/iocon.rs b/chips/lpc55s6x/src/iocon.rs new file mode 100644 index 0000000000..a91916f50f --- /dev/null +++ b/chips/lpc55s6x/src/iocon.rs @@ -0,0 +1,4322 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use crate::gpio::LPCPin; +use kernel::utilities::registers::interfaces::Writeable; +use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite}; +use kernel::utilities::StaticRef; + +register_structs! { + /// I/O pin configuration (IOCON) + pub IoconRegisters { + /// Digital I/O control for port 0 pins PIO0_0 + (0x000 => pio0_0: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_1 + (0x004 => pio0_1: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_2 + (0x008 => pio0_2: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_3 + (0x00C => pio0_3: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_4 + (0x010 => pio0_4: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_5 + (0x014 => pio0_5: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_6 + (0x018 => pio0_6: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_7 + (0x01C => pio0_7: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_8 + (0x020 => pio0_8: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_9 + (0x024 => pio0_9: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_10 + (0x028 => pio0_10: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_11 + (0x02C => pio0_11: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_12 + (0x030 => pio0_12: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_13 + (0x034 => pio0_13: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_14 + (0x038 => pio0_14: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_15 + (0x03C => pio0_15: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_16 + (0x040 => pio0_16: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_17 + (0x044 => pio0_17: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_18 + (0x048 => pio0_18: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_19 + (0x04C => pio0_19: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_20 + (0x050 => pio0_20: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_21 + (0x054 => pio0_21: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_22 + (0x058 => pio0_22: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_23 + (0x05C => pio0_23: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_24 + (0x060 => pio0_24: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_25 + (0x064 => pio0_25: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_26 + (0x068 => pio0_26: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_27 + (0x06C => pio0_27: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_28 + (0x070 => pio0_28: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_29 + (0x074 => pio0_29: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_30 + (0x078 => pio0_30: ReadWrite), + /// Digital I/O control for port 0 pins PIO0_31 + (0x07C => pio0_31: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_0 + (0x080 => pio1_0: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_1 + (0x084 => pio1_1: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_2 + (0x088 => pio1_2: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_3 + (0x08C => pio1_3: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_4 + (0x090 => pio1_4: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_5 + (0x094 => pio1_5: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_6 + (0x098 => pio1_6: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_7 + (0x09C => pio1_7: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_8 + (0x0A0 => pio1_8: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_9 + (0x0A4 => pio1_9: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_10 + (0x0A8 => pio1_10: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_11 + (0x0AC => pio1_11: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_12 + (0x0B0 => pio1_12: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_13 + (0x0B4 => pio1_13: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_14 + (0x0B8 => pio1_14: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_15 + (0x0BC => pio1_15: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_16 + (0x0C0 => pio1_16: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_17 + (0x0C4 => pio1_17: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_18 + (0x0C8 => pio1_18: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_19 + (0x0CC => pio1_19: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_20 + (0x0D0 => pio1_20: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_21 + (0x0D4 => pio1_21: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_22 + (0x0D8 => pio1_22: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_23 + (0x0DC => pio1_23: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_24 + (0x0E0 => pio1_24: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_25 + (0x0E4 => pio1_25: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_26 + (0x0E8 => pio1_26: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_27 + (0x0EC => pio1_27: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_28 + (0x0F0 => pio1_28: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_29 + (0x0F4 => pio1_29: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_30 + (0x0F8 => pio1_30: ReadWrite), + /// Digital I/O control for port 1 pins PIO1_31 + (0x0FC => pio1_31: ReadWrite), + (0x100 => @END), + } +} +register_bitfields![u32, +PIO0_0 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_1 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_2 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_3 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_4 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_5 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_6 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_7 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_8 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_9 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_10 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_11 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_12 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_13 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Supply Selection bit. + SSEL OFFSET(11) NUMBITS(1) [ + /// 3V3 Signaling in I2C Mode. + _3V3SignalingInI2CMode = 0, + /// 1V8 Signaling in I2C Mode. + _1V8SignalingInI2CMode = 1 + ], + /// Controls input glitch filter. + FILTEROFF OFFSET(12) NUMBITS(1) [ + /// Filter enabled. + FilterEnabled = 0, + /// Filter disabled. + FilterDisabled = 1 + ], + /// Pull-up current source enable in I2C mode. + ECS OFFSET(13) NUMBITS(1) [ + /// Disabled. IO is in open drain cell. + DisabledIOIsInOpenDrainCell = 0, + /// Enabled. Pull resistor is conencted. + EnabledPullResistorIsConencted = 1 + ], + /// Switch between GPIO mode and I2C mode. + EGP OFFSET(14) NUMBITS(1) [ + /// I2C mode. + I2CMode = 0, + /// GPIO mode. + GPIOMode = 1 + ], + /// Configures I2C features for standard mode, fast mode, and Fast Mode Plus operati + I2CFILTER OFFSET(15) NUMBITS(1) [ + /// I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and + FAST_MODE = 0, + /// I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + I2C10NsGlitchFilterEnabledTypicallyUsedForHighSpeedModeI2C = 1 + ] +], +PIO0_14 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Supply Selection bit. + SSEL OFFSET(11) NUMBITS(1) [ + /// 3V3 Signaling in I2C Mode. + _3V3SignalingInI2CMode = 0, + /// 1V8 Signaling in I2C Mode. + _1V8SignalingInI2CMode = 1 + ], + /// Controls input glitch filter. + FILTEROFF OFFSET(12) NUMBITS(1) [ + /// Filter enabled. + FilterEnabled = 0, + /// Filter disabled. + FilterDisabled = 1 + ], + /// Pull-up current source enable in I2C mode. + ECS OFFSET(13) NUMBITS(1) [ + /// Disabled. IO is in open drain cell. + DisabledIOIsInOpenDrainCell = 0, + /// Enabled. Pull resistor is conencted. + EnabledPullResistorIsConencted = 1 + ], + /// Switch between GPIO mode and I2C mode. + EGP OFFSET(14) NUMBITS(1) [ + /// I2C mode. + I2CMode = 0, + /// GPIO mode. + GPIOMode = 1 + ], + /// Configures I2C features for standard mode, fast mode, and Fast Mode Plus operati + I2CFILTER OFFSET(15) NUMBITS(1) [ + /// I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and + FAST_MODE = 0, + /// I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + I2C10NsGlitchFilterEnabledTypicallyUsedForHighSpeedModeI2C = 1 + ] +], +PIO0_15 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_16 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_17 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_18 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_19 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_20 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_21 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_22 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_23 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO0_24 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_25 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_26 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_27 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_28 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_29 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_30 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO0_31 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_0 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_1 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_2 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_3 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_4 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_5 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_6 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_7 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_8 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_9 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_10 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_11 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_12 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_13 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_14 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_15 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_16 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_17 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_18 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_19 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ], + /// Analog switch input control. + ASW OFFSET(10) NUMBITS(1) [ + /// For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, + VALUE0 = 0, + /// For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 + VALUE1 = 1 + ] +], +PIO1_20 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_21 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_22 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_23 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_24 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_25 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_26 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_27 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_28 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_29 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_30 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +], +PIO1_31 [ + /// Selects pin function. + FUNC OFFSET(0) NUMBITS(4) [ + /// Alternative connection 0. + AlternativeConnection0 = 0, + /// Alternative connection 1. + AlternativeConnection1 = 1, + /// Alternative connection 2. + AlternativeConnection2 = 2, + /// Alternative connection 3. + AlternativeConnection3 = 3, + /// Alternative connection 4. + AlternativeConnection4 = 4, + /// Alternative connection 5. + AlternativeConnection5 = 5, + /// Alternative connection 6. + AlternativeConnection6 = 6, + /// Alternative connection 7. + AlternativeConnection7 = 7 + ], + /// Selects function mode (on-chip pull-up/pull-down resistor control). + MODE OFFSET(4) NUMBITS(2) [ + /// Inactive. Inactive (no pull-down/pull-up resistor enabled). + InactiveInactiveNoPullDownPullUpResistorEnabled = 0, + /// Pull-down. Pull-down resistor enabled. + PullDownPullDownResistorEnabled = 1, + /// Pull-up. Pull-up resistor enabled. + PullUpPullUpResistorEnabled = 2, + /// Repeater. Repeater mode. + RepeaterRepeaterMode = 3 + ], + /// Driver slew rate. + SLEW OFFSET(6) NUMBITS(1) [ + /// Standard-mode, output slew rate is slower. More outputs can be switched simultan + StandardModeOutputSlewRateIsSlowerMoreOutputsCanBeSwitchedSimultaneously = 0, + /// Fast-mode, output slew rate is faster. Refer to the appropriate specific device + FAST = 1 + ], + /// Input polarity. + INVERT OFFSET(7) NUMBITS(1) [ + /// Disabled. Input function is not inverted. + DisabledInputFunctionIsNotInverted = 0, + /// Enabled. Input is function inverted. + EnabledInputIsFunctionInverted = 1 + ], + /// Select Digital mode. + DIGIMODE OFFSET(8) NUMBITS(1) [ + /// Disable digital mode. Digital input set to 0. + DisableDigitalModeDigitalInputSetTo0 = 0, + /// Enable Digital mode. Digital input is enabled. + EnableDigitalModeDigitalInputIsEnabled = 1 + ], + /// Controls open-drain mode. + OD OFFSET(9) NUMBITS(1) [ + /// Normal. Normal push-pull output + NormalNormalPushPullOutput = 0, + /// Open-drain. Simulated open-drain output (high drive disabled). + OpenDrainSimulatedOpenDrainOutputHighDriveDisabled = 1 + ] +] +]; +pub(crate) const IOCON_BASE: StaticRef = + unsafe { StaticRef::new(0x50001000 as *const IoconRegisters) }; + +#[allow(dead_code)] +#[derive(Clone, Copy)] +pub enum Function { + GPIO = 0, + Alt1 = 1, + Alt2 = 2, + Alt3 = 3, + Alt4 = 4, + Alt5 = 5, + Alt6 = 6, + Alt7 = 7, +} + +#[allow(dead_code)] +#[derive(Clone, Copy)] +pub enum Pull { + None = 0b00, + Down = 0b01, + Up = 0b10, + Repeater = 0b11, +} + +#[allow(dead_code)] +#[derive(Clone, Copy)] +pub enum Slew { + Standard = 0, + Fast = 1, +} + +pub struct Config { + pub function: Function, + pub pull: Pull, + pub slew: Slew, + pub invert: bool, + pub digital_mode: bool, + pub open_drain: bool, +} + +pub struct Iocon { + registers: StaticRef, +} + +impl Iocon { + pub const fn new() -> Self { + Self { + registers: IOCON_BASE, + } + } + + pub fn configure_pin(&self, pin: LPCPin, config: Config) { + let standard_value = PIO0_0::FUNC.val(config.function as u32) + + PIO0_0::MODE.val(config.pull as u32) + + PIO0_0::DIGIMODE.val(config.digital_mode as u32); + + match pin { + LPCPin::P0_0 => self.registers.pio0_0.set(standard_value.into()), + LPCPin::P0_1 => self.registers.pio0_1.set(standard_value.into()), + // LPCPin::P0_2 => self.registers.pio0_2.set(standard_value.into()), + // LPCPin::P0_3 => self.registers.pio0_3.set(standard_value.into()), + // LPCPin::P0_4 => self.registers.pio0_4.set(standard_value.into()), + // LPCPin::P0_5 => self.registers.pio0_5.set(standard_value.into()), + // LPCPin::P0_6 => self.registers.pio0_6.set(standard_value.into()), + // LPCPin::P0_7 => self.registers.pio0_7.set(standard_value.into()), + // LPCPin::P0_8 => self.registers.pio0_8.set(standard_value.into()), + // LPCPin::P0_9 => self.registers.pio0_9.set(standard_value.into()), + // LPCPin::P0_10 => self.registers.pio0_10.set(standard_value.into()), + // LPCPin::P0_11 => self.registers.pio0_11.set(standard_value.into()), + // LPCPin::P0_12 => self.registers.pio0_12.set(standard_value.into()), + // LPCPin::P0_13 => self.registers.pio0_13.set(standard_value.into()), + // LPCPin::P0_14 => self.registers.pio0_14.set(standard_value.into()), + // LPCPin::P0_15 => self.registers.pio0_15.set(standard_value.into()), + // LPCPin::P0_16 => self.registers.pio0_16.set(standard_value.into()), + // LPCPin::P0_17 => self.registers.pio0_17.set(standard_value.into()), + // LPCPin::P0_18 => self.registers.pio0_18.set(standard_value.into()), + // LPCPin::P0_19 => self.registers.pio0_19.set(standard_value.into()), + // LPCPin::P0_20 => self.registers.pio0_20.set(standard_value.into()), + // LPCPin::P0_21 => self.registers.pio0_21.set(standard_value.into()), + // LPCPin::P0_22 => self.registers.pio0_22.set(standard_value.into()), + // LPCPin::P0_23 => self.registers.pio0_23.set(standard_value.into()), + // LPCPin::P0_24 => self.registers.pio0_24.set(standard_value.into()), + // LPCPin::P0_25 => self.registers.pio0_25.set(standard_value.into()), + // LPCPin::P0_26 => self.registers.pio0_26.set(standard_value.into()), + // LPCPin::P0_27 => self.registers.pio0_27.set(standard_value.into()), + // LPCPin::P0_28 => self.registers.pio0_28.set(standard_value.into()), + // LPCPin::P0_29 => self.registers.pio0_29.set(standard_value.into()), + // LPCPin::P0_30 => self.registers.pio0_30.set(standard_value.into()), + // LPCPin::P0_31 => self.registers.pio0_31.set(standard_value.into()), + // LPCPin::P1_0 => self.registers.pio1_0.set(standard_value.into()), + // LPCPin::P1_1 => self.registers.pio1_1.set(standard_value.into()), + // LPCPin::P1_2 => self.registers.pio1_2.set(standard_value.into()), + // LPCPin::P1_3 => self.registers.pio1_3.set(standard_value.into()), + LPCPin::P1_4 => self.registers.pio1_4.set(standard_value.into()), //BLUE LED ON THE BOARD + // LPCPin::P1_5 => self.registers.pio1_5.set(standard_value.into()), + LPCPin::P1_6 => self.registers.pio1_6.set(standard_value.into()), + // LPCPin::P1_7 => self.registers.pio1_7.set(standard_value.into()), + // LPCPin::P1_8 => self.registers.pio1_8.set(standard_value.into()), + LPCPin::P1_9 => self.registers.pio1_9.set(standard_value.into()), //USER BUTTON ON THE BOARD + // LPCPin::P1_10 => self.registers.pio1_10.set(standard_value.into()), + // LPCPin::P1_11 => self.registers.pio1_11.set(standard_value.into()), + // LPCPin::P1_12 => self.registers.pio1_12.set(standard_value.into()), + // LPCPin::P1_13 => self.registers.pio1_13.set(standard_value.into()), + // LPCPin::P1_14 => self.registers.pio1_14.set(standard_value.into()), + // LPCPin::P1_15 => self.registers.pio1_15.set(standard_value.into()), + // LPCPin::P1_16 => self.registers.pio1_16.set(standard_value.into()), + // LPCPin::P1_17 => self.registers.pio1_17.set(standard_value.into()), + // LPCPin::P1_18 => self.registers.pio1_18.set(standard_value.into()), + // LPCPin::P1_19 => self.registers.pio1_19.set(standard_value.into()), + // LPCPin::P1_20 => self.registers.pio1_20.set(standard_value.into()), + // LPCPin::P1_21 => self.registers.pio1_21.set(standard_value.into()), + // LPCPin::P1_22 => self.registers.pio1_22.set(standard_value.into()), + // LPCPin::P1_23 => self.registers.pio1_23.set(standard_value.into()), + // LPCPin::P1_24 => self.registers.pio1_24.set(standard_value.into()), + // LPCPin::P1_25 => self.registers.pio1_25.set(standard_value.into()), + // LPCPin::P1_26 => self.registers.pio1_26.set(standard_value.into()), + // LPCPin::P1_27 => self.registers.pio1_27.set(standard_value.into()), + // LPCPin::P1_28 => self.registers.pio1_28.set(standard_value.into()), + // LPCPin::P1_29 => self.registers.pio1_29.set(standard_value.into()), + // LPCPin::P1_30 => self.registers.pio1_30.set(standard_value.into()), + // LPCPin::P1_31 => self.registers.pio1_31.set(standard_value.into()), + _ => {} + } + } + + pub fn set_pull_none(&self, pin: LPCPin) { + let config = Config { + function: Function::GPIO, + pull: Pull::None, + slew: Slew::Standard, + invert: false, + digital_mode: true, + open_drain: false, + }; + self.configure_pin(pin, config); + } + + pub fn set_pull_up(&self, pin: LPCPin) { + let config = Config { + function: Function::GPIO, + pull: Pull::Up, + slew: Slew::Standard, + invert: false, + digital_mode: true, + open_drain: false, + }; + self.configure_pin(pin, config); + } + + pub fn set_pull_down(&self, pin: LPCPin) { + let config = Config { + function: Function::GPIO, + pull: Pull::Down, + slew: Slew::Standard, + invert: false, + digital_mode: true, + open_drain: false, + }; + self.configure_pin(pin, config); + } +} diff --git a/chips/lpc55s6x/src/lib.rs b/chips/lpc55s6x/src/lib.rs new file mode 100644 index 0000000000..ce569c3890 --- /dev/null +++ b/chips/lpc55s6x/src/lib.rs @@ -0,0 +1,122 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +#![no_std] +#![recursion_limit = "512"] + +use cortexm33::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM33, CortexMVariant}; + +pub mod chip; +pub mod clocks; +pub mod ctimer0; +pub mod gpio; +pub mod inputmux; +pub mod interrupts; +pub mod iocon; +pub mod pint; +// pub mod rtc; +// pub mod adc0; +pub mod syscon; + +extern "C" { + fn _estack(); +} + +#[cfg_attr( + all(target_arch = "arm", target_os = "none"), + link_section = ".vectors" +)] +#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)] +pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [ + _estack, + initialize_ram_jump_to_main, + unhandled_interrupt, + CortexM33::HARD_FAULT_HANDLER, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + CortexM33::SVC_HANDLER, + unhandled_interrupt, + unhandled_interrupt, + unhandled_interrupt, + CortexM33::SYSTICK_HANDLER, +]; + +#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")] +#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)] +pub static IRQS: [unsafe extern "C" fn(); 60] = [ + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, + CortexM33::GENERIC_ISR, +]; + +pub unsafe fn init() { + cortexm33::nvic::disable_all(); + cortexm33::nvic::clear_all_pending(); + + cortexm33::scb::set_vector_table_offset(core::ptr::addr_of!(BASE_VECTORS) as *const ()); + + cortexm33::nvic::enable_all(); +} diff --git a/chips/lpc55s6x/src/nvic.rs b/chips/lpc55s6x/src/nvic.rs new file mode 100644 index 0000000000..713c8d1735 --- /dev/null +++ b/chips/lpc55s6x/src/nvic.rs @@ -0,0 +1,23358 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::utilities::StaticRef; +use kernel::utilities::registers::{self, register_bitfields, register_structs, ReadOnly, ReadWrite, WriteOnly}; + +register_structs! { + /// no description available + NvicRegisters { + /// Interrupt Set Enable Register + (0x000 => iser_0: ReadWrite), + /// Interrupt Set Enable Register + (0x004 => iser_1: ReadWrite), + /// Interrupt Set Enable Register + (0x008 => iser_2: ReadWrite), + /// Interrupt Set Enable Register + (0x00C => iser_3: ReadWrite), + /// Interrupt Set Enable Register + (0x010 => iser_4: ReadWrite), + /// Interrupt Set Enable Register + (0x014 => iser_5: ReadWrite), + /// Interrupt Set Enable Register + (0x018 => iser_6: ReadWrite), + /// Interrupt Set Enable Register + (0x01C => iser_7: ReadWrite), + /// Interrupt Set Enable Register + (0x020 => iser_8: ReadWrite), + /// Interrupt Set Enable Register + (0x024 => iser_9: ReadWrite), + /// Interrupt Set Enable Register + (0x028 => iser_10: ReadWrite), + /// Interrupt Set Enable Register + (0x02C => iser_11: ReadWrite), + /// Interrupt Set Enable Register + (0x030 => iser_12: ReadWrite), + /// Interrupt Set Enable Register + (0x034 => iser_13: ReadWrite), + /// Interrupt Set Enable Register + (0x038 => iser_14: ReadWrite), + /// Interrupt Set Enable Register + (0x03C => iser_15: ReadWrite), + (0x040 => _reserved0), + /// Interrupt Clear Enable Register + (0x080 => icer_0: ReadWrite), + /// Interrupt Clear Enable Register + (0x084 => icer_1: ReadWrite), + /// Interrupt Clear Enable Register + (0x088 => icer_2: ReadWrite), + /// Interrupt Clear Enable Register + (0x08C => icer_3: ReadWrite), + /// Interrupt Clear Enable Register + (0x090 => icer_4: ReadWrite), + /// Interrupt Clear Enable Register + (0x094 => icer_5: ReadWrite), + /// Interrupt Clear Enable Register + (0x098 => icer_6: ReadWrite), + /// Interrupt Clear Enable Register + (0x09C => icer_7: ReadWrite), + /// Interrupt Clear Enable Register + (0x0A0 => icer_8: ReadWrite), + /// Interrupt Clear Enable Register + (0x0A4 => icer_9: ReadWrite), + /// Interrupt Clear Enable Register + (0x0A8 => icer_10: ReadWrite), + /// Interrupt Clear Enable Register + (0x0AC => icer_11: ReadWrite), + /// Interrupt Clear Enable Register + (0x0B0 => icer_12: ReadWrite), + /// Interrupt Clear Enable Register + (0x0B4 => icer_13: ReadWrite), + /// Interrupt Clear Enable Register + (0x0B8 => icer_14: ReadWrite), + /// Interrupt Clear Enable Register + (0x0BC => icer_15: ReadWrite), + (0x0C0 => _reserved1), + /// Interrupt Set Pending Register + (0x100 => ispr_0: ReadWrite), + /// Interrupt Set Pending Register + (0x104 => ispr_1: ReadWrite), + /// Interrupt Set Pending Register + (0x108 => ispr_2: ReadWrite), + /// Interrupt Set Pending Register + (0x10C => ispr_3: ReadWrite), + /// Interrupt Set Pending Register + (0x110 => ispr_4: ReadWrite), + /// Interrupt Set Pending Register + (0x114 => ispr_5: ReadWrite), + /// Interrupt Set Pending Register + (0x118 => ispr_6: ReadWrite), + /// Interrupt Set Pending Register + (0x11C => ispr_7: ReadWrite), + /// Interrupt Set Pending Register + (0x120 => ispr_8: ReadWrite), + /// Interrupt Set Pending Register + (0x124 => ispr_9: ReadWrite), + /// Interrupt Set Pending Register + (0x128 => ispr_10: ReadWrite), + /// Interrupt Set Pending Register + (0x12C => ispr_11: ReadWrite), + /// Interrupt Set Pending Register + (0x130 => ispr_12: ReadWrite), + /// Interrupt Set Pending Register + (0x134 => ispr_13: ReadWrite), + /// Interrupt Set Pending Register + (0x138 => ispr_14: ReadWrite), + /// Interrupt Set Pending Register + (0x13C => ispr_15: ReadWrite), + (0x140 => _reserved2), + /// Interrupt Clear Pending Register + (0x180 => icpr_0: ReadWrite), + /// Interrupt Clear Pending Register + (0x184 => icpr_1: ReadWrite), + /// Interrupt Clear Pending Register + (0x188 => icpr_2: ReadWrite), + /// Interrupt Clear Pending Register + (0x18C => icpr_3: ReadWrite), + /// Interrupt Clear Pending Register + (0x190 => icpr_4: ReadWrite), + /// Interrupt Clear Pending Register + (0x194 => icpr_5: ReadWrite), + /// Interrupt Clear Pending Register + (0x198 => icpr_6: ReadWrite), + /// Interrupt Clear Pending Register + (0x19C => icpr_7: ReadWrite), + /// Interrupt Clear Pending Register + (0x1A0 => icpr_8: ReadWrite), + /// Interrupt Clear Pending Register + (0x1A4 => icpr_9: ReadWrite), + /// Interrupt Clear Pending Register + (0x1A8 => icpr_10: ReadWrite), + /// Interrupt Clear Pending Register + (0x1AC => icpr_11: ReadWrite), + /// Interrupt Clear Pending Register + (0x1B0 => icpr_12: ReadWrite), + /// Interrupt Clear Pending Register + (0x1B4 => icpr_13: ReadWrite), + /// Interrupt Clear Pending Register + (0x1B8 => icpr_14: ReadWrite), + /// Interrupt Clear Pending Register + (0x1BC => icpr_15: ReadWrite), + (0x1C0 => _reserved3), + /// Interrupt Active Bit Register + (0x200 => iabr_0: ReadWrite), + /// Interrupt Active Bit Register + (0x204 => iabr_1: ReadWrite), + /// Interrupt Active Bit Register + (0x208 => iabr_2: ReadWrite), + /// Interrupt Active Bit Register + (0x20C => iabr_3: ReadWrite), + /// Interrupt Active Bit Register + (0x210 => iabr_4: ReadWrite), + /// Interrupt Active Bit Register + (0x214 => iabr_5: ReadWrite), + /// Interrupt Active Bit Register + (0x218 => iabr_6: ReadWrite), + /// Interrupt Active Bit Register + (0x21C => iabr_7: ReadWrite), + /// Interrupt Active Bit Register + (0x220 => iabr_8: ReadWrite), + /// Interrupt Active Bit Register + (0x224 => iabr_9: ReadWrite), + /// Interrupt Active Bit Register + (0x228 => iabr_10: ReadWrite), + /// Interrupt Active Bit Register + (0x22C => iabr_11: ReadWrite), + /// Interrupt Active Bit Register + (0x230 => iabr_12: ReadWrite), + /// Interrupt Active Bit Register + (0x234 => iabr_13: ReadWrite), + /// Interrupt Active Bit Register + (0x238 => iabr_14: ReadWrite), + /// Interrupt Active Bit Register + (0x23C => iabr_15: ReadWrite), + (0x240 => _reserved4), + /// Interrupt Target Non-secure Register + (0x280 => itns_0: ReadWrite), + /// Interrupt Target Non-secure Register + (0x284 => itns_1: ReadWrite), + /// Interrupt Target Non-secure Register + (0x288 => itns_2: ReadWrite), + /// Interrupt Target Non-secure Register + (0x28C => itns_3: ReadWrite), + /// Interrupt Target Non-secure Register + (0x290 => itns_4: ReadWrite), + /// Interrupt Target Non-secure Register + (0x294 => itns_5: ReadWrite), + /// Interrupt Target Non-secure Register + (0x298 => itns_6: ReadWrite), + /// Interrupt Target Non-secure Register + (0x29C => itns_7: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2A0 => itns_8: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2A4 => itns_9: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2A8 => itns_10: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2AC => itns_11: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2B0 => itns_12: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2B4 => itns_13: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2B8 => itns_14: ReadWrite), + /// Interrupt Target Non-secure Register + (0x2BC => itns_15: ReadWrite), + (0x2C0 => _reserved5), + /// Interrupt Priority Register + (0x300 => ipr_0: ReadWrite), + /// Interrupt Priority Register + (0x304 => ipr_1: ReadWrite), + /// Interrupt Priority Register + (0x308 => ipr_2: ReadWrite), + /// Interrupt Priority Register + (0x30C => ipr_3: ReadWrite), + /// Interrupt Priority Register + (0x310 => ipr_4: ReadWrite), + /// Interrupt Priority Register + (0x314 => ipr_5: ReadWrite), + /// Interrupt Priority Register + (0x318 => ipr_6: ReadWrite), + /// Interrupt Priority Register + (0x31C => ipr_7: ReadWrite), + /// Interrupt Priority Register + (0x320 => ipr_8: ReadWrite), + /// Interrupt Priority Register + (0x324 => ipr_9: ReadWrite), + /// Interrupt Priority Register + (0x328 => ipr_10: ReadWrite), + /// Interrupt Priority Register + (0x32C => ipr_11: ReadWrite), + /// Interrupt Priority Register + (0x330 => ipr_12: ReadWrite), + /// Interrupt Priority Register + (0x334 => ipr_13: ReadWrite), + /// Interrupt Priority Register + (0x338 => ipr_14: ReadWrite), + /// Interrupt Priority Register + (0x33C => ipr_15: ReadWrite), + /// Interrupt Priority Register + (0x340 => ipr_16: ReadWrite), + /// Interrupt Priority Register + (0x344 => ipr_17: ReadWrite), + /// Interrupt Priority Register + (0x348 => ipr_18: ReadWrite), + /// Interrupt Priority Register + (0x34C => ipr_19: ReadWrite), + /// Interrupt Priority Register + (0x350 => ipr_20: ReadWrite), + /// Interrupt Priority Register + (0x354 => ipr_21: ReadWrite), + /// Interrupt Priority Register + (0x358 => ipr_22: ReadWrite), + /// Interrupt Priority Register + (0x35C => ipr_23: ReadWrite), + /// Interrupt Priority Register + (0x360 => ipr_24: ReadWrite), + /// Interrupt Priority Register + (0x364 => ipr_25: ReadWrite), + /// Interrupt Priority Register + (0x368 => ipr_26: ReadWrite), + /// Interrupt Priority Register + (0x36C => ipr_27: ReadWrite), + /// Interrupt Priority Register + (0x370 => ipr_28: ReadWrite), + /// Interrupt Priority Register + (0x374 => ipr_29: ReadWrite), + /// Interrupt Priority Register + (0x378 => ipr_30: ReadWrite), + /// Interrupt Priority Register + (0x37C => ipr_31: ReadWrite), + /// Interrupt Priority Register + (0x380 => ipr_32: ReadWrite), + /// Interrupt Priority Register + (0x384 => ipr_33: ReadWrite), + /// Interrupt Priority Register + (0x388 => ipr_34: ReadWrite), + /// Interrupt Priority Register + (0x38C => ipr_35: ReadWrite), + /// Interrupt Priority Register + (0x390 => ipr_36: ReadWrite), + /// Interrupt Priority Register + (0x394 => ipr_37: ReadWrite), + /// Interrupt Priority Register + (0x398 => ipr_38: ReadWrite), + /// Interrupt Priority Register + (0x39C => ipr_39: ReadWrite), + /// Interrupt Priority Register + (0x3A0 => ipr_40: ReadWrite), + /// Interrupt Priority Register + (0x3A4 => ipr_41: ReadWrite), + /// Interrupt Priority Register + (0x3A8 => ipr_42: ReadWrite), + /// Interrupt Priority Register + (0x3AC => ipr_43: ReadWrite), + /// Interrupt Priority Register + (0x3B0 => ipr_44: ReadWrite), + /// Interrupt Priority Register + (0x3B4 => ipr_45: ReadWrite), + /// Interrupt Priority Register + (0x3B8 => ipr_46: ReadWrite), + /// Interrupt Priority Register + (0x3BC => ipr_47: ReadWrite), + /// Interrupt Priority Register + (0x3C0 => ipr_48: ReadWrite), + /// Interrupt Priority Register + (0x3C4 => ipr_49: ReadWrite), + /// Interrupt Priority Register + (0x3C8 => ipr_50: ReadWrite), + /// Interrupt Priority Register + (0x3CC => ipr_51: ReadWrite), + /// Interrupt Priority Register + (0x3D0 => ipr_52: ReadWrite), + /// Interrupt Priority Register + (0x3D4 => ipr_53: ReadWrite), + /// Interrupt Priority Register + (0x3D8 => ipr_54: ReadWrite), + /// Interrupt Priority Register + (0x3DC => ipr_55: ReadWrite), + /// Interrupt Priority Register + (0x3E0 => ipr_56: ReadWrite), + /// Interrupt Priority Register + (0x3E4 => ipr_57: ReadWrite), + /// Interrupt Priority Register + (0x3E8 => ipr_58: ReadWrite), + /// Interrupt Priority Register + (0x3EC => ipr_59: ReadWrite), + /// Interrupt Priority Register + (0x3F0 => ipr_60: ReadWrite), + /// Interrupt Priority Register + (0x3F4 => ipr_61: ReadWrite), + /// Interrupt Priority Register + (0x3F8 => ipr_62: ReadWrite), + /// Interrupt Priority Register + (0x3FC => ipr_63: ReadWrite), + /// Interrupt Priority Register + (0x400 => ipr_64: ReadWrite), + /// Interrupt Priority Register + (0x404 => ipr_65: ReadWrite), + /// Interrupt Priority Register + (0x408 => ipr_66: ReadWrite), + /// Interrupt Priority Register + (0x40C => ipr_67: ReadWrite), + /// Interrupt Priority Register + (0x410 => ipr_68: ReadWrite), + /// Interrupt Priority Register + (0x414 => ipr_69: ReadWrite), + /// Interrupt Priority Register + (0x418 => ipr_70: ReadWrite), + /// Interrupt Priority Register + (0x41C => ipr_71: ReadWrite), + /// Interrupt Priority Register + (0x420 => ipr_72: ReadWrite), + /// Interrupt Priority Register + (0x424 => ipr_73: ReadWrite), + /// Interrupt Priority Register + (0x428 => ipr_74: ReadWrite), + /// Interrupt Priority Register + (0x42C => ipr_75: ReadWrite), + /// Interrupt Priority Register + (0x430 => ipr_76: ReadWrite), + /// Interrupt Priority Register + (0x434 => ipr_77: ReadWrite), + /// Interrupt Priority Register + (0x438 => ipr_78: ReadWrite), + /// Interrupt Priority Register + (0x43C => ipr_79: ReadWrite), + /// Interrupt Priority Register + (0x440 => ipr_80: ReadWrite), + /// Interrupt Priority Register + (0x444 => ipr_81: ReadWrite), + /// Interrupt Priority Register + (0x448 => ipr_82: ReadWrite), + /// Interrupt Priority Register + (0x44C => ipr_83: ReadWrite), + /// Interrupt Priority Register + (0x450 => ipr_84: ReadWrite), + /// Interrupt Priority Register + (0x454 => ipr_85: ReadWrite), + /// Interrupt Priority Register + (0x458 => ipr_86: ReadWrite), + /// Interrupt Priority Register + (0x45C => ipr_87: ReadWrite), + /// Interrupt Priority Register + (0x460 => ipr_88: ReadWrite), + /// Interrupt Priority Register + (0x464 => ipr_89: ReadWrite), + /// Interrupt Priority Register + (0x468 => ipr_90: ReadWrite), + /// Interrupt Priority Register + (0x46C => ipr_91: ReadWrite), + /// Interrupt Priority Register + (0x470 => ipr_92: ReadWrite), + /// Interrupt Priority Register + (0x474 => ipr_93: ReadWrite), + /// Interrupt Priority Register + (0x478 => ipr_94: ReadWrite), + /// Interrupt Priority Register + (0x47C => ipr_95: ReadWrite), + /// Interrupt Priority Register + (0x480 => ipr_96: ReadWrite), + /// Interrupt Priority Register + (0x484 => ipr_97: ReadWrite), + /// Interrupt Priority Register + (0x488 => ipr_98: ReadWrite), + /// Interrupt Priority Register + (0x48C => ipr_99: ReadWrite), + /// Interrupt Priority Register + (0x490 => ipr_100: ReadWrite), + /// Interrupt Priority Register + (0x494 => ipr_101: ReadWrite), + /// Interrupt Priority Register + (0x498 => ipr_102: ReadWrite), + /// Interrupt Priority Register + (0x49C => ipr_103: ReadWrite), + /// Interrupt Priority Register + (0x4A0 => ipr_104: ReadWrite), + /// Interrupt Priority Register + (0x4A4 => ipr_105: ReadWrite), + /// Interrupt Priority Register + (0x4A8 => ipr_106: ReadWrite), + /// Interrupt Priority Register + (0x4AC => ipr_107: ReadWrite), + /// Interrupt Priority Register + (0x4B0 => ipr_108: ReadWrite), + /// Interrupt Priority Register + (0x4B4 => ipr_109: ReadWrite), + /// Interrupt Priority Register + (0x4B8 => ipr_110: ReadWrite), + /// Interrupt Priority Register + (0x4BC => ipr_111: ReadWrite), + /// Interrupt Priority Register + (0x4C0 => ipr_112: ReadWrite), + /// Interrupt Priority Register + (0x4C4 => ipr_113: ReadWrite), + /// Interrupt Priority Register + (0x4C8 => ipr_114: ReadWrite), + /// Interrupt Priority Register + (0x4CC => ipr_115: ReadWrite), + /// Interrupt Priority Register + (0x4D0 => ipr_116: ReadWrite), + /// Interrupt Priority Register + (0x4D4 => ipr_117: ReadWrite), + /// Interrupt Priority Register + (0x4D8 => ipr_118: ReadWrite), + /// Interrupt Priority Register + (0x4DC => ipr_119: ReadWrite), + (0x4E0 => _reserved6), + /// Software Trigger Interrupt Register + (0xE00 => stir: WriteOnly), + (0xE04 => @END), + } +} +register_bitfields![u32, +STIR [ + /// Interrupt ID of the interrupt to trigger, in the range 0-479. + INTID OFFSET(0) NUMBITS(9) [] +], +ISER[0] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[1] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[2] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[3] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[4] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[5] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[6] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[7] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[8] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[9] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[10] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[11] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[12] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[13] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[14] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISER[15] [ + /// Interrupt set-enable bits. + SETENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt set-enable bits. + SETENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[0] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[1] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[2] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[3] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[4] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[5] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[6] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[7] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[8] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[9] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[10] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[11] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[12] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[13] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[14] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ICER[15] [ + /// Interrupt clear-enable bits. + CLRENA0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ], + /// Interrupt clear-enable bits. + CLRENA31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m disabled + WriteNoEffectReadInterrupt32nMDisabled = 0, + /// Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + WriteEnableInterrupt32nMReadInterrupt32nMEnabled = 1 + ] +], +ISPR[0] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[1] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[2] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[3] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[4] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[5] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[6] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[7] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[8] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[9] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[10] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[11] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[12] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[13] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[14] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ISPR[15] [ + /// Interrupt set-pending bits. + SETPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ], + /// Interrupt set-pending bits. + SETPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + WritePendInterrupt32nMReadInterrupt32nMPending = 1 + ] +], +ICPR[0] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[1] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[2] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[3] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[4] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[5] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[6] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[7] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[8] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[9] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[10] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[11] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[12] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[13] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[14] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +ICPR[15] [ + /// Interrupt clear-pending bits. + CLRPEND0 OFFSET(0) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND1 OFFSET(1) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND2 OFFSET(2) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND3 OFFSET(3) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND4 OFFSET(4) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND5 OFFSET(5) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND6 OFFSET(6) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND7 OFFSET(7) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND8 OFFSET(8) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND9 OFFSET(9) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND10 OFFSET(10) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND11 OFFSET(11) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND12 OFFSET(12) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND13 OFFSET(13) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND14 OFFSET(14) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND15 OFFSET(15) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND16 OFFSET(16) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND17 OFFSET(17) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND18 OFFSET(18) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND19 OFFSET(19) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND20 OFFSET(20) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND21 OFFSET(21) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND22 OFFSET(22) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND23 OFFSET(23) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND24 OFFSET(24) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND25 OFFSET(25) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND26 OFFSET(26) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND27 OFFSET(27) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND28 OFFSET(28) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND29 OFFSET(29) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND30 OFFSET(30) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ], + /// Interrupt clear-pending bits. + CLRPEND31 OFFSET(31) NUMBITS(1) [ + /// Write: No effect; Read: Interrupt 32n+m is not pending + WriteNoEffectReadInterrupt32nMIsNotPending = 0, + /// Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + WriteClearPendingStateOfInterrupt32nMReadInterrupt32nMIsPending = 1 + ] +], +IABR[0] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[1] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[2] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[3] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[4] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[5] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[6] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[7] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[8] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[9] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[10] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[11] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[12] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[13] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[14] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +IABR[15] [ + /// Active state bits. + ACTIVE0 OFFSET(0) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE1 OFFSET(1) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE2 OFFSET(2) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE3 OFFSET(3) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE4 OFFSET(4) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE5 OFFSET(5) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE6 OFFSET(6) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE7 OFFSET(7) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE8 OFFSET(8) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE9 OFFSET(9) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE10 OFFSET(10) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE11 OFFSET(11) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE12 OFFSET(12) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE13 OFFSET(13) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE14 OFFSET(14) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE15 OFFSET(15) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE16 OFFSET(16) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE17 OFFSET(17) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE18 OFFSET(18) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE19 OFFSET(19) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE20 OFFSET(20) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE21 OFFSET(21) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE22 OFFSET(22) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE23 OFFSET(23) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE24 OFFSET(24) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE25 OFFSET(25) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE26 OFFSET(26) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE27 OFFSET(27) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE28 OFFSET(28) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE29 OFFSET(29) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE30 OFFSET(30) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ], + /// Active state bits. + ACTIVE31 OFFSET(31) NUMBITS(1) [ + /// The interrupt is not active. + TheInterruptIsNotActive = 0, + /// The interrupt is active. + TheInterruptIsActive = 1 + ] +], +ITNS[0] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[1] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[2] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[3] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[4] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[5] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[6] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[7] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[8] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[9] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[10] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[11] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[12] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[13] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[14] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +ITNS[15] [ + /// Interrupt Targets Non-secure bits. + INTS0 OFFSET(0) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS1 OFFSET(1) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS2 OFFSET(2) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS3 OFFSET(3) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS4 OFFSET(4) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS5 OFFSET(5) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS6 OFFSET(6) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS7 OFFSET(7) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS8 OFFSET(8) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS9 OFFSET(9) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS10 OFFSET(10) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS11 OFFSET(11) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS12 OFFSET(12) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS13 OFFSET(13) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS14 OFFSET(14) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS15 OFFSET(15) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS16 OFFSET(16) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS17 OFFSET(17) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS18 OFFSET(18) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS19 OFFSET(19) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS20 OFFSET(20) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS21 OFFSET(21) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS22 OFFSET(22) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS23 OFFSET(23) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS24 OFFSET(24) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS25 OFFSET(25) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS26 OFFSET(26) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS27 OFFSET(27) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS28 OFFSET(28) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS29 OFFSET(29) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS30 OFFSET(30) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ], + /// Interrupt Targets Non-secure bits. + INTS31 OFFSET(31) NUMBITS(1) [ + /// The interrupt targets Secure state. + TheInterruptTargetsSecureState = 0, + /// The interrupt targets Non-secure state. + TheInterruptTargetsNonSecureState = 1 + ] +], +IPR[0] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[1] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[2] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[3] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[4] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[5] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[6] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[7] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[8] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[9] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[10] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[11] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[12] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[13] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[14] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[15] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[16] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[17] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[18] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[19] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[20] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[21] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[22] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[23] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[24] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[25] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[26] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[27] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[28] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[29] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[30] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[31] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[32] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[33] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[34] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[35] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[36] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[37] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[38] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[39] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[40] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[41] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[42] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[43] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[44] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[45] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[46] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[47] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[48] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[49] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[50] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[51] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[52] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[53] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[54] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[55] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[56] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[57] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[58] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[59] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[60] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[61] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[62] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[63] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[64] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[65] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[66] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[67] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[68] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[69] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[70] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[71] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[72] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[73] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[74] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[75] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[76] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[77] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[78] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[79] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[80] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[81] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[82] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[83] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[84] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[85] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[86] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[87] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[88] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[89] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[90] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[91] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[92] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[93] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[94] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[95] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[96] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[97] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[98] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[99] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[100] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[101] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[102] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[103] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[104] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[105] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[106] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[107] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[108] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[109] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[110] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[111] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[112] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[113] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[114] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[115] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[116] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[117] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[118] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +], +IPR[119] [ + /// no description available + PRI_0 OFFSET(0) NUMBITS(8) [], + /// no description available + PRI_1 OFFSET(8) NUMBITS(8) [], + /// no description available + PRI_2 OFFSET(16) NUMBITS(8) [], + /// no description available + PRI_3 OFFSET(24) NUMBITS(8) [] +] +]; +const NVIC_BASE: StaticRef = + unsafe { StaticRef::new(0xE000E100 as *const NvicRegisters) }; diff --git a/chips/lpc55s6x/src/pint.rs b/chips/lpc55s6x/src/pint.rs new file mode 100644 index 0000000000..8aa9a60d79 --- /dev/null +++ b/chips/lpc55s6x/src/pint.rs @@ -0,0 +1,587 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::utilities::cells::OptionalCell; +use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; +use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite, WriteOnly}; +use kernel::utilities::StaticRef; + +register_structs! { + pub PintRegisters { + /// Pin Interrupt Mode register + (0x00 => isel: ReadWrite), + /// Pin interrupt level or rising edge interrupt enable register + (0x04 => ienr: ReadWrite), + /// Pin interrupt level or rising edge interrupt set register + (0x08 => sienr: WriteOnly), + /// Pin interrupt level (rising edge interrupt) clear register + (0x0C => cienr: WriteOnly), + /// Pin interrupt active level or falling edge interrupt enable register + (0x10 => ienf: ReadWrite), + /// Pin interrupt active level or falling edge interrupt set register + (0x14 => sienf: WriteOnly), + /// Pin interrupt active level or falling edge interrupt clear register + (0x18 => cienf: WriteOnly), + /// Pin interrupt rising edge register + (0x1C => rise: ReadWrite), + /// Pin interrupt falling edge register + (0x20 => fall: ReadWrite), + /// Pin interrupt status register + (0x24 => ist: ReadWrite), + (0x28 => @END), + } +} +register_bitfields![u32, +ISEL [ + /// Selects the interrupt mode for each pin interrupt. Bit n configures the pin inte + PMODE OFFSET(0) NUMBITS(8) [] +], +IENR [ + /// Enables the rising edge or level interrupt for each pin interrupt. Bit n configu + ENRL OFFSET(0) NUMBITS(8) [] +], +SIENR [ + /// Ones written to this address set bits in the IENR, thus enabling interrupts. Bit + SETENRL OFFSET(0) NUMBITS(8) [] +], +CIENR [ + /// Ones written to this address clear bits in the IENR, thus disabling the interrup + CENRL OFFSET(0) NUMBITS(8) [] +], +IENF [ + /// Enables the falling edge or configures the active level interrupt for each pin i + ENAF OFFSET(0) NUMBITS(8) [] +], +SIENF [ + /// Ones written to this address set bits in the IENF, thus enabling interrupts. Bit + SETENAF OFFSET(0) NUMBITS(8) [] +], +CIENF [ + /// Ones written to this address clears bits in the IENF, thus disabling interrupts. + CENAF OFFSET(0) NUMBITS(8) [] +], +RISE [ + /// Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSEL + RDET OFFSET(0) NUMBITS(8) [] +], +FALL [ + /// Falling edge detect. Bit n detects the falling edge of the pin selected in PINTS + FDET OFFSET(0) NUMBITS(8) [] +], +IST [ + /// Pin interrupt status. Bit n returns the status, clears the edge interrupt, or in + PSTAT OFFSET(0) NUMBITS(8) [] +], +PMCTRL [ + /// Specifies whether the 8 pin interrupts are controlled by the pin interrupt funct + SEL_PMATCH OFFSET(0) NUMBITS(1) [ + /// Pin interrupt. Interrupts are driven in response to the standard pin interrupt f + PinInterruptInterruptsAreDrivenInResponseToTheStandardPinInterruptFunction = 0, + /// Pattern match. Interrupts are driven in response to pattern matches. + PatternMatchInterruptsAreDrivenInResponseToPatternMatches = 1 + ], + /// Enables the RXEV output to the CPU and/or to a GPIO output when the specified bo + ENA_RXEV OFFSET(1) NUMBITS(1) [ + /// Disabled. RXEV output to the CPU is disabled. + DisabledRXEVOutputToTheCPUIsDisabled = 0, + /// Enabled. RXEV output to the CPU is enabled. + EnabledRXEVOutputToTheCPUIsEnabled = 1 + ], + /// This field displays the current state of pattern matches. A 1 in any bit of this + PMAT OFFSET(24) NUMBITS(8) [] +], +PMSRC [ + /// Selects the input source for bit slice 0 + SRC0 OFFSET(8) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice0 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice0 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice0 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice0 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice0 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice0 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice0 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice0 = 7 + ], + /// Selects the input source for bit slice 1 + SRC1 OFFSET(11) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice1 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice1 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice1 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice1 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice1 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice1 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice1 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice1 = 7 + ], + /// Selects the input source for bit slice 2 + SRC2 OFFSET(14) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice2 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice2 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice2 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice2 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice2 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice2 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice2 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice2 = 7 + ], + /// Selects the input source for bit slice 3 + SRC3 OFFSET(17) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice3 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice3 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice3 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice3 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice3 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice3 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice3 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice3 = 7 + ], + /// Selects the input source for bit slice 4 + SRC4 OFFSET(20) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice4 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice4 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice4 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice4 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice4 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice4 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice4 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice4 = 7 + ], + /// Selects the input source for bit slice 5 + SRC5 OFFSET(23) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice5 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice5 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice5 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice5 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice5 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice5 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice5 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice5 = 7 + ], + /// Selects the input source for bit slice 6 + SRC6 OFFSET(26) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice6 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice6 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice6 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice6 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice6 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice6 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice6 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice6 = 7 + ], + /// Selects the input source for bit slice 7 + SRC7 OFFSET(29) NUMBITS(3) [ + /// Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit + Input0SelectsThePinSelectedInThePINTSEL0RegisterAsTheSourceToBitSlice7 = 0, + /// Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit + Input1SelectsThePinSelectedInThePINTSEL1RegisterAsTheSourceToBitSlice7 = 1, + /// Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit + Input2SelectsThePinSelectedInThePINTSEL2RegisterAsTheSourceToBitSlice7 = 2, + /// Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit + Input3SelectsThePinSelectedInThePINTSEL3RegisterAsTheSourceToBitSlice7 = 3, + /// Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit + Input4SelectsThePinSelectedInThePINTSEL4RegisterAsTheSourceToBitSlice7 = 4, + /// Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit + Input5SelectsThePinSelectedInThePINTSEL5RegisterAsTheSourceToBitSlice7 = 5, + /// Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit + Input6SelectsThePinSelectedInThePINTSEL6RegisterAsTheSourceToBitSlice7 = 6, + /// Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit + Input7SelectsThePinSelectedInThePINTSEL7RegisterAsTheSourceToBitSlice7 = 7 + ] +], +PMCFG [ + /// Determines whether slice 0 is an endpoint. + PROD_ENDPTS0 OFFSET(0) NUMBITS(1) [ + /// No effect. Slice 0 is not an endpoint. + NoEffectSlice0IsNotAnEndpoint = 0, + /// endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 i + ENDPOINT = 1 + ], + /// Determines whether slice 1 is an endpoint. + PROD_ENDPTS1 OFFSET(1) NUMBITS(1) [ + /// No effect. Slice 1 is not an endpoint. + NoEffectSlice1IsNotAnEndpoint = 0, + /// endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 i + ENDPOINT = 1 + ], + /// Determines whether slice 2 is an endpoint. + PROD_ENDPTS2 OFFSET(2) NUMBITS(1) [ + /// No effect. Slice 2 is not an endpoint. + NoEffectSlice2IsNotAnEndpoint = 0, + /// endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 i + ENDPOINT = 1 + ], + /// Determines whether slice 3 is an endpoint. + PROD_ENDPTS3 OFFSET(3) NUMBITS(1) [ + /// No effect. Slice 3 is not an endpoint. + NoEffectSlice3IsNotAnEndpoint = 0, + /// endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 i + ENDPOINT = 1 + ], + /// Determines whether slice 4 is an endpoint. + PROD_ENDPTS4 OFFSET(4) NUMBITS(1) [ + /// No effect. Slice 4 is not an endpoint. + NoEffectSlice4IsNotAnEndpoint = 0, + /// endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 i + ENDPOINT = 1 + ], + /// Determines whether slice 5 is an endpoint. + PROD_ENDPTS5 OFFSET(5) NUMBITS(1) [ + /// No effect. Slice 5 is not an endpoint. + NoEffectSlice5IsNotAnEndpoint = 0, + /// endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 i + ENDPOINT = 1 + ], + /// Determines whether slice 6 is an endpoint. + PROD_ENDPTS6 OFFSET(6) NUMBITS(1) [ + /// No effect. Slice 6 is not an endpoint. + NoEffectSlice6IsNotAnEndpoint = 0, + /// endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 i + ENDPOINT = 1 + ], + /// Specifies the match contribution condition for bit slice 0. + CFG0 OFFSET(8) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 1. + CFG1 OFFSET(11) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 2. + CFG2 OFFSET(14) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 3. + CFG3 OFFSET(17) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 4. + CFG4 OFFSET(20) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 5. + CFG5 OFFSET(23) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 6. + CFG6 OFFSET(26) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ], + /// Specifies the match contribution condition for bit slice 7. + CFG7 OFFSET(29) NUMBITS(3) [ + /// Constant HIGH. This bit slice always contributes to a product term match. + ConstantHIGHThisBitSliceAlwaysContributesToAProductTermMatch = 0, + /// Sticky rising edge. Match occurs if a rising edge on the specified input has occ + STICKY_RISING_EDGE = 1, + /// Sticky falling edge. Match occurs if a falling edge on the specified input has o + STICKY_FALLING_EDGE = 2, + /// Sticky rising or falling edge. Match occurs if either a rising or falling edge o + STICKY_RISING_FALLING_EDGE = 3, + /// High level. Match (for this bit slice) occurs when there is a high level on the + HIGH_LEVEL = 4, + /// Low level. Match occurs when there is a low level on the specified input. + LowLevelMatchOccursWhenThereIsALowLevelOnTheSpecifiedInput = 5, + /// Constant 0. This bit slice never contributes to a match (should be used to disab + CONSTANT_ZERO = 6, + /// Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when e + EVENT = 7 + ] +] +]; +pub(crate) const PINT_BASE: StaticRef = + unsafe { StaticRef::new(0x50004000 as *const PintRegisters) }; + +#[derive(Clone, Copy)] +pub enum Edge { + Rising, + Falling, + Both, +} + +pub struct Pint<'a> { + registers: StaticRef, + clients: [OptionalCell<&'a dyn kernel::hil::gpio::Client>; 8], +} + +// pub static PINT: Pint = Pint::new(); + +impl<'a> Pint<'a> { + pub const fn new() -> Self { + Self { + registers: PINT_BASE, + clients: [ + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + OptionalCell::empty(), + ], + } + } + + // pub fn find_and_take_channel(&self) -> Option { + // for i in 0..self.clients.len() { + // if self.clients[i].is_none() { + // self.clients[i].put(unsafe {core::mem::transmute(&())}); + // return Some(i as u8); + // } + // } + + // None + // } + + // pub fn select_pin(&self, pin_num: usize, channel: u8) { + // if channel < 8 { + // inputmux::INPUTMUX.pintsel[channel as usize].set(pin_num as u32); + // } + // } + + pub fn set_client(&self, channel: u8, client: &'a dyn kernel::hil::gpio::Client) { + if channel < 8 { + self.clients[channel as usize].replace(client); + } + } + + pub fn configure_interrupt(&self, channel: usize, edge: Edge) { + if channel < 8 { + let mask = 1 << channel; + + self.registers.isel.modify(ISEL::PMODE.val(!mask)); + // self.registers.rise.modify(RISE::RDET.val(mask)); + // self.registers.fall.modify(FALL::FDET.val(mask)); + + match edge { + Edge::Rising => { + self.registers.sienr.write(SIENR::SETENRL.val(mask)); + self.registers.cienf.write(CIENF::CENAF.val(mask)); + } + Edge::Falling => { + self.registers.sienf.write(SIENF::SETENAF.val(mask)); + self.registers.cienr.write(CIENR::CENRL.val(mask)); + } + Edge::Both => { + self.registers.sienr.write(SIENR::SETENRL.val(mask)); + self.registers.sienf.write(SIENF::SETENAF.val(mask)); + } + } + } + + // self.registers.isel.modify(ISEL::PMODE.val(1)); + // self.registers.ienr.modify(IENR::ENRL.val(1)); + // self.registers.ienf.modify(IENF::ENAF.val(1)); + } + + // pub fn disable_and_free_channel(&mut self, channel: u8) { + // if channel < 8 { + // let mask = 1 << channel; + + // self.registers.cienr.write(CIENR::CENRL.val(mask)); + // self.registers.cienf.write(CIENF::CENAF.val(mask)); + // // self.clients[channel as usize].take(); + // } + + // } + + pub fn handle_interrupt(&self) { + let status = self.registers.ist.get(); + + self.registers.rise.write(RISE::RDET.val(status)); + self.registers.fall.write(FALL::FDET.val(status)); + + // self.registers.ist.get(); + + // let blue_led = GpioPin::new(LPCPin::P1_6); + + for i in 0..8 { + if (status & (1 << i)) != 0 { + self.registers.ist.write(IST::PSTAT.val(1 << i)); + // hprintln!("IST loop {}", self.registers.ist.get()); + + self.clients[i].map(|client| client.fired()); + } + } + + // blue_led.toggle(); + // Self::delay_ms(1000); + // blue_led.toggle(); + + // self.configure_interrupt(0, Edge::Rising); + } + + pub fn disable_interrupt(&self, channel: usize) { + if channel < 8 { + let mask = 1 << channel; + + self.registers.cienr.write(CIENR::CENRL.val(mask)); + self.registers.cienf.write(CIENF::CENAF.val(mask)); + } + } + + pub fn read_interrupt(&self) -> u32 { + self.registers.rise.get() + } +} diff --git a/chips/lpc55s6x/src/rtc.rs b/chips/lpc55s6x/src/rtc.rs new file mode 100644 index 0000000000..a8192fbb21 --- /dev/null +++ b/chips/lpc55s6x/src/rtc.rs @@ -0,0 +1,186 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::hil; +use kernel::utilities::cells::OptionalCell; +use kernel::utilities::registers::{ + self, register_bitfields, register_structs, ReadOnly, ReadWrite, WriteOnly, +}; +use kernel::utilities::StaticRef; + +register_structs! { + /// Real-Time Clock (RTC) + RtcRegisters { + /// RTC control register + (0x000 => ctrl: ReadWrite), + /// RTC match register + (0x004 => match: ReadWrite), + /// RTC counter register + (0x008 => count: ReadWrite), + /// High-resolution/wake-up timer control register + (0x00C => wake: ReadWrite), + /// Sub-second counter register + (0x010 => subsec: ReadWrite), + (0x014 => _reserved0), + /// General Purpose register + (0x040 => gpreg_0: ReadWrite), + /// General Purpose register + (0x044 => gpreg_1: ReadWrite), + /// General Purpose register + (0x048 => gpreg_2: ReadWrite), + /// General Purpose register + (0x04C => gpreg_3: ReadWrite), + /// General Purpose register + (0x050 => gpreg_4: ReadWrite), + /// General Purpose register + (0x054 => gpreg_5: ReadWrite), + /// General Purpose register + (0x058 => gpreg_6: ReadWrite), + /// General Purpose register + (0x05C => gpreg_7: ReadWrite), + (0x060 => @END), + } +} +register_bitfields![u32, +CTRL [ + /// Software reset control + SWRESET OFFSET(0) NUMBITS(1) [ + /// Not in reset. The RTC is not held in reset. This bit must be cleared prior to co + NOT_IN_RESET = 0, + /// In reset. The RTC is held in reset. All register bits within the RTC will be for + IN_RESET = 1 + ], + /// RTC 1 Hz timer alarm flag status. + ALARM1HZ OFFSET(2) NUMBITS(1) [ + /// No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect + NoMatchNoMatchHasOccurredOnThe1HzRTCTimerWritingA0HasNoEffect = 0, + /// Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates + MATCH = 1 + ], + /// RTC 1 kHz timer wake-up flag status. + WAKE1KHZ OFFSET(3) NUMBITS(1) [ + /// Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + RunTheRTC1KHzTimerIsRunningWritingA0HasNoEffect = 0, + /// Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag gener + TIMEOUT = 1 + ], + /// RTC 1 Hz timer alarm enable for Deep power-down. + ALARMDPD_EN OFFSET(4) NUMBITS(1) [ + /// Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power + DisableAMatchOnThe1HzRTCTimerWillNotBringThePartOutOfDeepPowerDownMode = 0, + /// Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode + EnableAMatchOnThe1HzRTCTimerBringThePartOutOfDeepPowerDownMode = 1 + ], + /// RTC 1 kHz timer wake-up enable for Deep power-down. + WAKEDPD_EN OFFSET(5) NUMBITS(1) [ + /// Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep powe + DisableAMatchOnThe1KHzRTCTimerWillNotBringThePartOutOfDeepPowerDownMode = 0, + /// Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mod + EnableAMatchOnThe1KHzRTCTimerBringThePartOutOfDeepPowerDownMode = 1 + ], + /// RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + RTC1KHZ_EN OFFSET(6) NUMBITS(1) [ + /// Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep powe + DisableAMatchOnThe1KHzRTCTimerWillNotBringThePartOutOfDeepPowerDownMode = 0, + /// Enable. The 1 kHz RTC timer is enabled. + EnableThe1KHzRTCTimerIsEnabled = 1 + ], + /// RTC enable. + RTC_EN OFFSET(7) NUMBITS(1) [ + /// Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is di + DISABLE = 0, + /// Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit mus + ENABLE = 1 + ], + /// RTC oscillator power-down control. + RTC_OSC_PD OFFSET(8) NUMBITS(1) [ + /// See RTC_OSC_BYPASS + SeeRTC_OSC_BYPASS = 0, + /// RTC oscillator is powered-down. + RTCOscillatorIsPoweredDown = 1 + ], + /// RTC oscillator bypass control. + RTC_OSC_BYPASS OFFSET(9) NUMBITS(1) [ + /// The RTC Oscillator operates normally as a crystal oscillator with the crystal co + USED = 0, + /// The RTC Oscillator is in bypass mode. In this mode a clock can be directly input + BYPASS = 1 + ], + /// RTC Sub-second counter control. + RTC_SUBSEC_ENA OFFSET(10) NUMBITS(1) [ + /// The sub-second counter (if implemented) is disabled. This bit is cleared by a sy + POWER_UP = 0, + /// The 32 KHz sub-second counter is enabled (if implemented). Counting commences on + POWERED_DOWN = 1 + ] +], +MATCH [ + /// Contains the match value against which the 1 Hz RTC timer will be compared to se + MATVAL OFFSET(0) NUMBITS(32) [] +], +COUNT [ + /// A read reflects the current value of the main, 1 Hz RTC timer. A write loads a n + VAL OFFSET(0) NUMBITS(32) [] +], +WAKE [ + /// A read reflects the current value of the high-resolution/wake-up timer. A write + VAL OFFSET(0) NUMBITS(16) [] +], +SUBSEC [ + /// A read reflects the current value of the 32KHz sub-second counter. This counter + SUBSEC OFFSET(0) NUMBITS(15) [] +], +GPREG0 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG1 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG2 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG3 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG4 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG5 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG6 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +], +GPREG7 [ + /// Data retained during Deep power-down mode or loss of main power as long as VBAT + GPDATA OFFSET(0) NUMBITS(32) [] +] +]; +const RTC_BASE: StaticRef = + unsafe { StaticRef::new(0x4002C000 as *const RtcRegisters) }; + +pub struct Rtc<'a> { + registers: StaticRef, + client: OptionalCell<&'a dyn hil::time::AlarmClient>, +} + +impl<'a> Rtc<'a> { + pub const fn new() -> Rtc<'a> { + Rtc { + registers: RTC_BASE, + client: OptionalCell::empty(), + } + } + + fn enable_interrupt(&self) { + self.registers + } +} diff --git a/chips/lpc55s6x/src/syscon.rs b/chips/lpc55s6x/src/syscon.rs new file mode 100644 index 0000000000..0f9bef9f36 --- /dev/null +++ b/chips/lpc55s6x/src/syscon.rs @@ -0,0 +1,3106 @@ +// Licensed under the Apache License, Version 2.0 or the MIT License. +// SPDX-License-Identifier: Apache-2.0 OR MIT +// Copyright Tock Contributors 2025. + +use kernel::utilities::registers::{ + register_bitfields, register_structs, ReadOnly, ReadWrite, WriteOnly, +}; +use kernel::utilities::StaticRef; + +register_structs! { + /// SYSCON + pub SysconRegisters { + /// Memory Remap control register + (0x000 => memoryremap: ReadWrite), + (0x004 => _reserved0), + /// AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest + (0x010 => ahbmatprio: ReadWrite), + (0x014 => _reserved1), + /// System tick calibration for secure part of CPU0 + (0x038 => cpu0stckcal: ReadWrite), + /// System tick calibration for non-secure part of CPU0 + (0x03C => cpu0nstckcal: ReadWrite), + /// System tick calibration for CPU1 + (0x040 => cpu1stckcal: ReadWrite), + (0x044 => _reserved2), + /// NMI Source Select + (0x048 => nmisrc: ReadWrite), + (0x04C => _reserved3), + /// Peripheral reset control 0 + (0x100 => pub presetctrl0: ReadWrite), + /// Peripheral reset control 1 + (0x104 => presetctrl1: ReadWrite), + /// Peripheral reset control 2 + (0x108 => presetctrl2: ReadWrite), + (0x10C => _reserved4), + /// Peripheral reset control set register + (0x120 => presetctrlset_0: ReadWrite), + /// Peripheral reset control set register + (0x124 => presetctrlset_1: ReadWrite), + /// Peripheral reset control set register + (0x128 => presetctrlset_2: ReadWrite), + (0x12C => _reserved5), + /// Peripheral reset control clear register + (0x140 => presetctrlclr_0: ReadWrite), + /// Peripheral reset control clear register + (0x144 => presetctrlclr_1: ReadWrite), + /// Peripheral reset control clear register + (0x148 => presetctrlclr_2: ReadWrite), + (0x14C => _reserved6), + /// generate a software_reset + (0x160 => swr_reset: WriteOnly), + (0x164 => _reserved7), + /// AHB Clock control 0 + (0x200 => pub ahbclkctrl0: ReadWrite), + /// AHB Clock control 1 + (0x204 => pub ahbclkctrl1: ReadWrite), + /// AHB Clock control 2 + (0x208 => ahbclkctrl2: ReadWrite), + (0x20C => _reserved8), + /// Peripheral reset control register + (0x220 => pub ahbclkctrlset_0: ReadWrite), + /// Peripheral reset control register + (0x224 => ahbclkctrlset_1: ReadWrite), + /// Peripheral reset control register + (0x228 => ahbclkctrlset_2: ReadWrite), + (0x22C => _reserved9), + /// Peripheral reset control register + (0x240 => ahbclkctrlclr_0: ReadWrite), + /// Peripheral reset control register + (0x244 => ahbclkctrlclr_1: ReadWrite), + /// Peripheral reset control register + (0x248 => ahbclkctrlclr_2: ReadWrite), + (0x24C => _reserved10), + /// System Tick Timer for CPU0 source select + (0x260 => systickclksel0: ReadWrite), + /// System Tick Timer for CPU1 source select + (0x264 => systickclksel1: ReadWrite), + /// Trace clock source select + (0x268 => traceclksel: ReadWrite), + /// CTimer 0 clock source select + (0x26C => pub ctimerclksel0: ReadWrite), + /// CTimer 1 clock source select + (0x270 => ctimerclksel1: ReadWrite), + /// CTimer 2 clock source select + (0x274 => ctimerclksel2: ReadWrite), + /// CTimer 3 clock source select + (0x278 => ctimerclksel3: ReadWrite), + /// CTimer 4 clock source select + (0x27C => ctimerclksel4: ReadWrite), + /// Main clock A source select + (0x280 => mainclksela: ReadWrite), + /// Main clock source select + (0x284 => mainclkselb: ReadWrite), + /// CLKOUT clock source select + (0x288 => pub clkoutsel: ReadWrite), + (0x28C => _reserved11), + /// PLL0 clock source select + (0x290 => pll0clksel: ReadWrite), + /// PLL1 clock source select + (0x294 => pll1clksel: ReadWrite), + (0x298 => _reserved12), + /// ADC clock source select + (0x2A4 => adcclksel: ReadWrite), + /// FS USB clock source select + (0x2A8 => usb0clksel: ReadWrite), + (0x2AC => _reserved13), + /// Flexcomm Interface 0 clock source select for Fractional Rate Divider + (0x2B0 => pub fcclksel0: ReadWrite), + /// Flexcomm Interface 1 clock source select for Fractional Rate Divider + (0x2B4 => pub fcclksel1: ReadWrite), + /// Flexcomm Interface 2 clock source select for Fractional Rate Divider + (0x2B8 => pub fcclksel2: ReadWrite), + /// Flexcomm Interface 3 clock source select for Fractional Rate Divider + (0x2BC => pub fcclksel3: ReadWrite), + /// Flexcomm Interface 4 clock source select for Fractional Rate Divider + (0x2C0 => pub fcclksel4: ReadWrite), + /// Flexcomm Interface 5 clock source select for Fractional Rate Divider + (0x2C4 => pub fcclksel5: ReadWrite), + /// Flexcomm Interface 6 clock source select for Fractional Rate Divider + (0x2C8 => pub fcclksel6: ReadWrite), + /// Flexcomm Interface 7 clock source select for Fractional Rate Divider + (0x2CC => pub fcclksel7: ReadWrite), + /// HS LSPI clock source select + (0x2D0 => hslspiclksel: ReadWrite), + (0x2D4 => _reserved14), + /// MCLK clock source select + (0x2E0 => mclkclksel: ReadWrite), + (0x2E4 => _reserved15), + /// SCTimer/PWM clock source select + (0x2F0 => sctclksel: ReadWrite), + (0x2F4 => _reserved16), + /// SDIO clock source select + (0x2F8 => sdioclksel: ReadWrite), + (0x2FC => _reserved17), + /// System Tick Timer divider for CPU0 + (0x300 => systickclkdiv0: ReadWrite), + /// System Tick Timer divider for CPU1 + (0x304 => systickclkdiv1: ReadWrite), + /// TRACE clock divider + (0x308 => traceclkdiv: ReadWrite), + (0x30C => _reserved18), + /// Fractional rate divider for flexcomm 0 + (0x320 => flexfrg0ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 1 + (0x324 => flexfrg1ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 2 + (0x328 => flexfrg2ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 3 + (0x32C => flexfrg3ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 4 + (0x330 => flexfrg4ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 5 + (0x334 => flexfrg5ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 6 + (0x338 => flexfrg6ctrl: ReadWrite), + /// Fractional rate divider for flexcomm 7 + (0x33C => flexfrg7ctrl: ReadWrite), + (0x340 => _reserved19), + /// System clock divider + (0x380 => ahbclkdiv: ReadWrite), + /// CLKOUT clock divider + (0x384 => clkoutdiv: ReadWrite), + /// FRO_HF (96MHz) clock divider + (0x388 => frohfdiv: ReadWrite), + /// WDT clock divider + (0x38C => wdtclkdiv: ReadWrite), + (0x390 => _reserved20), + /// ADC clock divider + (0x394 => adcclkdiv: ReadWrite), + /// USB0 Clock divider + (0x398 => usb0clkdiv: ReadWrite), + (0x39C => _reserved21), + /// I2S MCLK clock divider + (0x3AC => mclkdiv: ReadWrite), + (0x3B0 => _reserved22), + /// SCT/PWM clock divider + (0x3B4 => sctclkdiv: ReadWrite), + (0x3B8 => _reserved23), + /// SDIO clock divider + (0x3BC => sdioclkdiv: ReadWrite), + (0x3C0 => _reserved24), + /// PLL0 clock divider + (0x3C4 => pll0clkdiv: ReadWrite), + (0x3C8 => _reserved25), + /// Control clock configuration registers access (like xxxDIV, xxxSEL) + (0x3FC => clockgenupdatelockout: ReadWrite), + /// FMC configuration register + (0x400 => fmccr: ReadWrite), + (0x404 => _reserved26), + /// USB0 need clock control + (0x40C => usb0needclkctrl: ReadWrite), + /// USB0 need clock status + (0x410 => usb0needclkstat: ReadWrite), + (0x414 => _reserved27), + /// FMCflush control + (0x41C => fmcflush: WriteOnly), + /// MCLK control + (0x420 => mclkio: ReadWrite), + /// USB1 need clock control + (0x424 => usb1needclkctrl: ReadWrite), + /// USB1 need clock status + (0x428 => usb1needclkstat: ReadWrite), + (0x42C => _reserved28), + /// SDIO CCLKIN phase and delay control + (0x460 => sdioclkctrl: ReadWrite), + (0x464 => _reserved29), + /// PLL1 550m control + (0x560 => pll1ctrl: ReadWrite), + /// PLL1 550m status + (0x564 => pll1stat: ReadWrite), + /// PLL1 550m N divider + (0x568 => pll1ndec: ReadWrite), + /// PLL1 550m M divider + (0x56C => pll1mdec: ReadWrite), + /// PLL1 550m P divider + (0x570 => pll1pdec: ReadWrite), + (0x574 => _reserved30), + /// PLL0 550m control + (0x580 => pll0ctrl: ReadWrite), + /// PLL0 550m status + (0x584 => pll0stat: ReadWrite), + /// PLL0 550m N divider + (0x588 => pll0ndec: ReadWrite), + /// PLL0 550m P divider + (0x58C => pll0pdec: ReadWrite), + /// PLL0 Spread Spectrum Wrapper control register 0 + (0x590 => pll0sscg0: ReadWrite), + /// PLL0 Spread Spectrum Wrapper control register 1 + (0x594 => pll0sscg1: ReadWrite), + (0x598 => _reserved31), + /// Functional retention control register + (0x704 => funcretentionctrl: ReadWrite), + (0x708 => _reserved32), + /// CPU Control for multiple processors + (0x800 => cpuctrl: ReadWrite), + /// Coprocessor Boot Address + (0x804 => cpboot: ReadWrite), + (0x808 => _reserved33), + /// CPU Status + (0x80C => cpstat: ReadWrite), + (0x810 => _reserved34), + /// Various system clock controls : Flash clock (48 MHz) control, clocks to Frequenc + (0xA18 => clock_ctrl: ReadWrite), + (0xA1C => _reserved35), + /// Comparator Interrupt control + (0xB10 => comp_int_ctrl: ReadWrite), + /// Comparator Interrupt status + (0xB14 => comp_int_status: ReadWrite), + (0xB18 => _reserved36), + /// Control automatic clock gating + (0xE04 => autoclkgateoverride: ReadWrite), + /// Enable bypass of the first stage of synchonization inside GPIO_INT module + (0xE08 => gpiopsync: ReadWrite), + (0xE0C => _reserved37), + /// Control write access to security registers. + (0xFA0 => debug_lock_en: ReadWrite), + /// Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. + (0xFA4 => debug_features: ReadWrite), + /// Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE r + (0xFA8 => debug_features_dp: ReadWrite), + (0xFAC => _reserved38), + /// block quiddikey/PUF all index. + (0xFBC => key_block: WriteOnly), + /// Debug authentication BEACON register + (0xFC0 => debug_auth_beacon: ReadWrite), + (0xFC4 => _reserved39), + /// CPUs configuration register + (0xFD4 => cpucfg: ReadWrite), + (0xFD8 => _reserved40), + /// Device ID + (0xFF8 => device_id0: ReadOnly), + /// Chip revision ID and Number + (0xFFC => dieid: ReadOnly), + (0x1000 => @END), + } +} +register_bitfields![u32, +MEMORYREMAP [ + /// Select the location of the vector table :. + MAP OFFSET(0) NUMBITS(2) [ + /// Vector Table in ROM. + VectorTableInROM = 0, + /// Vector Table in RAM. + VectorTableInRAM = 1, + /// Vector Table in Flash. + VectorTableInFlash = 2 + ] +], +AHBMATPRIO [ + /// CPU0 C-AHB bus. + PRI_CPU0_CBUS OFFSET(0) NUMBITS(2) [], + /// CPU0 S-AHB bus. + PRI_CPU0_SBUS OFFSET(2) NUMBITS(2) [], + /// CPU1 C-AHB bus. + PRI_CPU1_CBUS OFFSET(4) NUMBITS(2) [], + /// CPU1 S-AHB bus. + PRI_CPU1_SBUS OFFSET(6) NUMBITS(2) [], + /// USB-FS.(USB0) + PRI_USB_FS OFFSET(8) NUMBITS(2) [], + /// DMA0 controller priority. + PRI_SDMA0 OFFSET(10) NUMBITS(2) [], + /// SDIO. + PRI_SDIO OFFSET(16) NUMBITS(2) [], + /// PQ (HW Accelerator). + PRI_PQ OFFSET(18) NUMBITS(2) [], + /// HASH_AES. + PRI_HASH_AES OFFSET(20) NUMBITS(2) [], + /// USB-HS.(USB1) + PRI_USB_HS OFFSET(22) NUMBITS(2) [], + /// DMA1 controller priority. + PRI_SDMA1 OFFSET(24) NUMBITS(2) [] +], +CPU0STCKCAL [ + /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If th + TENMS OFFSET(0) NUMBITS(24) [], + /// Initial value for the Systick timer. + SKEW OFFSET(24) NUMBITS(1) [], + /// Indicates whether the device provides a reference clock to the processor: 0 = re + NOREF OFFSET(25) NUMBITS(1) [] +], +CPU0NSTCKCAL [ + /// Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If + TENMS OFFSET(0) NUMBITS(24) [], + /// Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS + SKEW OFFSET(24) NUMBITS(1) [], + /// Initial value for the Systick timer. + NOREF OFFSET(25) NUMBITS(1) [] +], +CPU1STCKCAL [ + /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If th + TENMS OFFSET(0) NUMBITS(24) [], + /// Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS + SKEW OFFSET(24) NUMBITS(1) [], + /// Indicates whether the device provides a reference clock to the processor: 0 = re + NOREF OFFSET(25) NUMBITS(1) [] +], +NMISRC [ + /// The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) fo + IRQCPU0 OFFSET(0) NUMBITS(6) [], + /// The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) fo + IRQCPU1 OFFSET(8) NUMBITS(6) [], + /// Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected + NMIENCPU1 OFFSET(30) NUMBITS(1) [], + /// Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected + NMIENCPU0 OFFSET(31) NUMBITS(1) [] +], +PRESETCTRL0 [ + /// ROM reset control. + ROM_RST OFFSET(1) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SRAM Controller 1 reset control. + SRAM_CTRL1_RST OFFSET(3) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SRAM Controller 2 reset control. + SRAM_CTRL2_RST OFFSET(4) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SRAM Controller 3 reset control. + SRAM_CTRL3_RST OFFSET(5) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SRAM Controller 4 reset control. + SRAM_CTRL4_RST OFFSET(6) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Flash controller reset control. + FLASH_RST OFFSET(7) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FMC controller reset control. + FMC_RST OFFSET(8) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Input Mux reset control. + MUX_RST OFFSET(11) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// I/O controller reset control. + IOCON_RST OFFSET(13) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO0 reset control. + GPIO0_RST OFFSET(14) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO1 reset control. + GPIO1_RST OFFSET(15) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO2 reset control. + GPIO2_RST OFFSET(16) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO3 reset control. + GPIO3_RST OFFSET(17) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Pin interrupt (PINT) reset control. + PINT_RST OFFSET(18) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Group interrupt (GINT) reset control. + GINT_RST OFFSET(19) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// DMA0 reset control. + DMA0_RST OFFSET(20) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// CRCGEN reset control. + CRCGEN_RST OFFSET(21) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Watchdog Timer reset control. + WWDT_RST OFFSET(22) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Real Time Clock (RTC) reset control. + RTC_RST OFFSET(23) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Inter CPU communication Mailbox reset control. + MAILBOX_RST OFFSET(26) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// ADC reset control. + ADC_RST OFFSET(27) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ] +], +PRESETCTRLX0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRL1 [ + /// MRT reset control. + MRT_RST OFFSET(0) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// OS Event Timer reset control. + OSTIMER_RST OFFSET(1) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SCT reset control. + SCT_RST OFFSET(2) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SCTIPU reset control. + SCTIPU_RST OFFSET(6) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// UTICK reset control. + UTICK_RST OFFSET(10) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC0 reset control. + FC0_RST OFFSET(11) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC1 reset control. + FC1_RST OFFSET(12) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC2 reset control. + FC2_RST OFFSET(13) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC3 reset control. + FC3_RST OFFSET(14) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC4 reset control. + FC4_RST OFFSET(15) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC5 reset control. + FC5_RST OFFSET(16) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC6 reset control. + FC6_RST OFFSET(17) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// FC7 reset control. + FC7_RST OFFSET(18) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Timer 2 reset control. + TIMER2_RST OFFSET(22) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB0 DEV reset control. + USB0_DEV_RST OFFSET(25) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Timer 0 reset control. + TIMER0_RST OFFSET(26) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Timer 1 reset control. + TIMER1_RST OFFSET(27) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ] +], +PRESETCTRLX1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRL2 [ + /// DMA1 reset control. + DMA1_RST OFFSET(1) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Comparator reset control. + COMP_RST OFFSET(2) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SDIO reset control. + SDIO_RST OFFSET(3) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB1 Host reset control. + USB1_HOST_RST OFFSET(4) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB1 dev reset control. + USB1_DEV_RST OFFSET(5) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB1 RAM reset control. + USB1_RAM_RST OFFSET(6) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB1 PHY reset control. + USB1_PHY_RST OFFSET(7) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Frequency meter reset control. + FREQME_RST OFFSET(8) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// RNG reset control. + RNG_RST OFFSET(13) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// SYSCTL Block reset. + SYSCTL_RST OFFSET(15) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB0 Host Master reset control. + USB0_HOSTM_RST OFFSET(16) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// USB0 Host Slave reset control. + USB0_HOSTS_RST OFFSET(17) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// HASH_AES reset control. + HASH_AES_RST OFFSET(18) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Power Quad reset control. + PQ_RST OFFSET(19) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// PLU LUT reset control. + PLULUT_RST OFFSET(20) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Timer 3 reset control. + TIMER3_RST OFFSET(21) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Timer 4 reset control. + TIMER4_RST OFFSET(22) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// PUF reset control reset control. + PUF_RST OFFSET(23) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// Casper reset control. + CASPER_RST OFFSET(24) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// analog control reset control. + ANALOG_CTRL_RST OFFSET(27) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// HS LSPI reset control. + HS_LSPI_RST OFFSET(28) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO secure reset control. + GPIO_SEC_RST OFFSET(29) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ], + /// GPIO secure int reset control. + GPIO_SEC_INT_RST OFFSET(30) NUMBITS(1) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Bloc is reset. + BlocIsReset = 1 + ] +], +PRESETCTRLX2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +SWR_RESET [ + /// Write 0x5A00_0001 to generate a software_reset. + SWR_RESET OFFSET(0) NUMBITS(32) [ + /// Bloc is not reset. + BlocIsNotReset = 0, + /// Generate a software reset. + GenerateASoftwareReset = 1509949441 + ] +], +pub AHBCLKCTRL0 [ + /// Enables the clock for the ROM. + ROM OFFSET(1) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SRAM Controller 1. + SRAM_CTRL1 OFFSET(3) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SRAM Controller 2. + SRAM_CTRL2 OFFSET(4) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SRAM Controller 3. + SRAM_CTRL3 OFFSET(5) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SRAM Controller 4. + SRAM_CTRL4 OFFSET(6) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Flash controller. + FLASH OFFSET(7) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FMC controller. + FMC OFFSET(8) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Input Mux. + MUX OFFSET(11) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the I/O controller. + IOCON OFFSET(13) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO0. + GPIO0 OFFSET(14) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO1. + GPIO1 OFFSET(15) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO2. + GPIO2 OFFSET(16) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO3. + GPIO3 OFFSET(17) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Pin interrupt (PINT). + PINT OFFSET(18) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Group interrupt (GINT). + GINT OFFSET(19) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the DMA0. + DMA0 OFFSET(20) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the CRCGEN. + CRCGEN OFFSET(21) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Watchdog Timer. + WWDT OFFSET(22) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Real Time Clock (RTC). + RTC OFFSET(23) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Inter CPU communication Mailbox. + MAILBOX OFFSET(26) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the ADC. + ADC OFFSET(27) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ] +], +AHBCLKCTRLX0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub AHBCLKCTRL1 [ + /// Enables the clock for the MRT. + MRT OFFSET(0) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the OS Event Timer. + OSTIMER OFFSET(1) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SCT. + SCT OFFSET(2) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the UTICK. + UTICK OFFSET(10) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC0. + FC0 OFFSET(11) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC1. + FC1 OFFSET(12) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC2. + FC2 OFFSET(13) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC3. + FC3 OFFSET(14) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC4. + FC4 OFFSET(15) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC5. + FC5 OFFSET(16) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC6. + FC6 OFFSET(17) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the FC7. + FC7 OFFSET(18) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Timer 2. + TIMER2 OFFSET(22) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB0 DEV. + USB0_DEV OFFSET(25) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Timer 0. + TIMER0 OFFSET(26) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Timer 1. + TIMER1 OFFSET(27) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ] +], +AHBCLKCTRLX1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRL2 [ + /// Enables the clock for the DMA1. + DMA1 OFFSET(1) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Comparator. + COMP OFFSET(2) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the SDIO. + SDIO OFFSET(3) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB1 Host. + USB1_HOST OFFSET(4) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB1 dev. + USB1_DEV OFFSET(5) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB1 RAM. + USB1_RAM OFFSET(6) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB1 PHY. + USB1_PHY OFFSET(7) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Frequency meter. + FREQME OFFSET(8) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the RNG. + RNG OFFSET(13) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// SYSCTL block clock. + SYSCTL OFFSET(15) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB0 Host Master. + USB0_HOSTM OFFSET(16) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the USB0 Host Slave. + USB0_HOSTS OFFSET(17) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the HASH_AES. + HASH_AES OFFSET(18) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Power Quad. + PQ OFFSET(19) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the PLU LUT. + PLULUT OFFSET(20) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Timer 3. + TIMER3 OFFSET(21) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Timer 4. + TIMER4 OFFSET(22) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the PUF reset control. + PUF OFFSET(23) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the Casper. + CASPER OFFSET(24) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the analog control. + ANALOG_CTRL OFFSET(27) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the HS LSPI. + HS_LSPI OFFSET(28) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO secure. + GPIO_SEC OFFSET(29) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ], + /// Enables the clock for the GPIO secure int. + GPIO_SEC_INT OFFSET(30) NUMBITS(1) [ + /// Disable Clock. + DisableClock = 0, + /// Enable Clock. + EnableClock = 1 + ] +], +AHBCLKCTRLX2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +SYSTICKCLKSEL0 [ + /// System Tick Timer for CPU0 source select. + SEL OFFSET(0) NUMBITS(3) [ + /// System Tick 0 divided clock. + SystemTick0DividedClock = 0, + /// FRO 1MHz clock. + FRO1MHzClock = 1, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 2, + /// No clock. + NoClock = 3 + ] +], +SYSTICKCLKSELX0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +SYSTICKCLKSEL1 [ + /// System Tick Timer for CPU1 source select. + SEL OFFSET(0) NUMBITS(3) [ + /// System Tick 1 divided clock. + SystemTick1DividedClock = 0, + /// FRO 1MHz clock. + FRO1MHzClock = 1, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 2, + /// No clock. + NoClock = 3 + ] +], +SYSTICKCLKSELX1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +TRACECLKSEL [ + /// Trace clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Trace divided clock. + TraceDividedClock = 0, + /// FRO 1MHz clock. + FRO1MHzClock = 1, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 2, + /// No clock. + NoClock = 3 + ] +], +pub CTIMERCLKSEL0 [ + /// CTimer 0 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6 + ] +], +CTIMERCLKSELX0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +CTIMERCLKSEL1 [ + /// CTimer 1 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6 + ] +], +CTIMERCLKSELX1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +CTIMERCLKSEL2 [ + /// CTimer 2 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6 + ] +], +CTIMERCLKSELX2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +CTIMERCLKSEL3 [ + /// CTimer 3 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6 + ] +], +CTIMERCLKSELX3 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +CTIMERCLKSEL4 [ + /// CTimer 4 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6 + ] +], +CTIMERCLKSELX4 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +MAINCLKSELA [ + /// Main clock A source select. + SEL OFFSET(0) NUMBITS(3) [ + /// FRO 12 MHz clock. + FRO12MHzClock = 0, + /// CLKIN clock. + CLKINClock = 1, + /// FRO 1MHz clock. + FRO1MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3 + ] +], +MAINCLKSELB [ + /// Main clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main Clock A. + MainClockA = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// PLL1 clock. + PLL1Clock = 2, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 3 + ] +], +pub CLKOUTSEL [ + /// CLKOUT clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// CLKIN clock. + CLKINClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// PLL1 clock. + PLL1Clock = 5, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +PLL0CLKSEL [ + /// PLL0 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// FRO 12 MHz clock. + FRO12MHzClock = 0, + /// CLKIN clock. + CLKINClock = 1, + /// FRO 1MHz clock. + FRO1MHzClock = 2, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 3, + /// No clock. + NoClock = 4 + ] +], +PLL1CLKSEL [ + /// PLL1 clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// FRO 12 MHz clock. + FRO12MHzClock = 0, + /// CLKIN clock. + CLKINClock = 1, + /// FRO 1MHz clock. + FRO1MHzClock = 2, + /// Oscillator 32kHz clock. + Oscillator32kHzClock = 3, + /// No clock. + NoClock = 4 + ] +], +ADCCLKSEL [ + /// ADC clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// FRO 96 MHz clock. + FRO96MHzClock = 2, + /// No clock. + NoClock = 4 + ] +], +USB0CLKSEL [ + /// FS USB clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// PLL1 clock. + PLL1Clock = 5 + ] +], +pub FCCLKSEL [ + /// Flexcomm Interface 0 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL1 [ + /// Flexcomm Interface 1 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL2 [ + /// Flexcomm Interface 2 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL3 [ + /// Flexcomm Interface 3 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX3 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL4 [ + /// Flexcomm Interface 4 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX4 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL5 [ + /// Flexcomm Interface 5 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX5 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL6 [ + /// Flexcomm Interface 6 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX6 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub FCCLKSEL7 [ + /// Flexcomm Interface 7 clock source select for Fractional Rate Divider. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// MCLK clock. + MCLKClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6, + /// No clock. + NoClock = 7 + ] +], +FCCLKSELX7 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +HSLSPICLKSEL [ + /// HS LSPI clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// system PLL divided clock. + SystemPLLDividedClock = 1, + /// FRO 12 MHz clock. + FRO12MHzClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// FRO 1MHz clock. + FRO1MHzClock = 4, + /// No clock. + NoClock = 5, + /// Oscillator 32 kHz clock. + Oscillator32KHzClock = 6 + ] +], +MCLKCLKSEL [ + /// MCLK clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// FRO 96 MHz clock. + FRO96MHzClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 4 + ] +], +SCTCLKSEL [ + /// SCTimer/PWM clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// CLKIN clock. + CLKINClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// No clock. + NoClock = 4, + /// MCLK clock. + MCLKClock = 5 + ] +], +SDIOCLKSEL [ + /// SDIO clock source select. + SEL OFFSET(0) NUMBITS(3) [ + /// Main clock. + MainClock = 0, + /// PLL0 clock. + PLL0Clock = 1, + /// No clock. + NoClock = 2, + /// FRO 96 MHz clock. + FRO96MHzClock = 3, + /// PLL1 clock. + PLL1Clock = 5 + ] +], +SYSTICKCLKDIV0 [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +SYSTICKCLKDIV1 [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +TRACECLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +FLEXFRG0CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG1CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG2CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG3CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL3 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG4CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL4 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG5CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL5 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG6CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL6 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +FLEXFRG7CTRL [ + /// Denominator of the fractional rate divider. + DIV OFFSET(0) NUMBITS(8) [], + /// Numerator of the fractional rate divider. + MULT OFFSET(8) NUMBITS(8) [] +], +FLEXFRGXCTRL7 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +CLKOUTDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +FROHFDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +WDTCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(6) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +ADCCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(3) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +USB0CLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +MCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +SCTCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +SDIOCLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +PLL0CLKDIV [ + /// Clock divider value. + DIV OFFSET(0) NUMBITS(8) [], + /// Resets the divider counter. + RESET OFFSET(29) NUMBITS(1) [ + /// Divider is not reset. + DividerIsNotReset = 0, + /// Divider is reset. + DividerIsReset = 1 + ], + /// Halts the divider counter. + HALT OFFSET(30) NUMBITS(1) [ + /// Divider clock is running. + DividerClockIsRunning = 0, + /// Divider clock is stoped. + DividerClockIsStoped = 1 + ], + /// Divider status flag. + REQFLAG OFFSET(31) NUMBITS(1) [ + /// Divider clock is stable. + DividerClockIsStable = 0, + /// Clock frequency is not stable. + ClockFrequencyIsNotStable = 1 + ] +], +CLOCKGENUPDATELOCKOUT [ + /// Control clock configuration registers access (like xxxDIV, xxxSEL). + CLOCKGENUPDATELOCKOUT OFFSET(0) NUMBITS(32) [ + /// all hardware clock configruration are freeze. + AllHardwareClockConfigrurationAreFreeze = 0, + /// update all clock configuration. + UpdateAllClockConfiguration = 1 + ] +], +FMCCR [ + /// Instruction fetch configuration. + FETCHCFG OFFSET(0) NUMBITS(2) [ + /// Instruction fetches from flash are not buffered. + InstructionFetchesFromFlashAreNotBuffered = 0, + /// One buffer is used for all instruction fetches. + OneBufferIsUsedForAllInstructionFetches = 1, + /// All buffers may be used for instruction fetches. + AllBuffersMayBeUsedForInstructionFetches = 2 + ], + /// Data read configuration. + DATACFG OFFSET(2) NUMBITS(2) [ + /// Data accesses from flash are not buffered. + DataAccessesFromFlashAreNotBuffered = 0, + /// One buffer is used for all data accesses. + OneBufferIsUsedForAllDataAccesses = 1, + /// All buffers can be used for data accesses. + AllBuffersCanBeUsedForDataAccesses = 2 + ], + /// Acceleration enable. + ACCEL OFFSET(4) NUMBITS(1) [ + /// Flash acceleration is disabled. + FlashAccelerationIsDisabled = 0, + /// Flash acceleration is enabled. + FlashAccelerationIsEnabled = 1 + ], + /// Prefetch enable. + PREFEN OFFSET(5) NUMBITS(1) [ + /// No instruction prefetch is performed. + NoInstructionPrefetchIsPerformed = 0, + /// Instruction prefetch is enabled. + InstructionPrefetchIsEnabled = 1 + ], + /// Prefetch override. + PREFOVR OFFSET(6) NUMBITS(1) [ + /// Any previously initiated prefetch will be completed. + AnyPreviouslyInitiatedPrefetchWillBeCompleted = 0, + /// Any previously initiated prefetch will be aborted, and the next flash line follo + OVERRIDE = 1 + ], + /// Flash memory access time. + FLASHTIM OFFSET(12) NUMBITS(4) [ + /// 1 system clock flash access time (for system clock rates up to 11 MHz). + _1SystemClockFlashAccessTimeForSystemClockRatesUpTo11MHz = 0, + /// 2 system clocks flash access time (for system clock rates up to 22 MHz). + _2SystemClocksFlashAccessTimeForSystemClockRatesUpTo22MHz = 1, + /// 3 system clocks flash access time (for system clock rates up to 33 MHz). + _3SystemClocksFlashAccessTimeForSystemClockRatesUpTo33MHz = 2, + /// 4 system clocks flash access time (for system clock rates up to 44 MHz). + _4SystemClocksFlashAccessTimeForSystemClockRatesUpTo44MHz = 3, + /// 5 system clocks flash access time (for system clock rates up to 55 MHz). + _5SystemClocksFlashAccessTimeForSystemClockRatesUpTo55MHz = 4, + /// 6 system clocks flash access time (for system clock rates up to 66 MHz). + _6SystemClocksFlashAccessTimeForSystemClockRatesUpTo66MHz = 5, + /// 7 system clocks flash access time (for system clock rates up to 77 MHz). + _7SystemClocksFlashAccessTimeForSystemClockRatesUpTo77MHz = 6, + /// 8 system clocks flash access time (for system clock rates up to 88 MHz). + _8SystemClocksFlashAccessTimeForSystemClockRatesUpTo88MHz = 7, + /// 9 system clocks flash access time (for system clock rates up to 100 MHz). + _9SystemClocksFlashAccessTimeForSystemClockRatesUpTo100MHz = 8, + /// 10 system clocks flash access time (for system clock rates up to 115 MHz). + _10SystemClocksFlashAccessTimeForSystemClockRatesUpTo115MHz = 9, + /// 11 system clocks flash access time (for system clock rates up to 130 MHz). + _11SystemClocksFlashAccessTimeForSystemClockRatesUpTo130MHz = 10, + /// 12 system clocks flash access time (for system clock rates up to 150 MHz). + _12SystemClocksFlashAccessTimeForSystemClockRatesUpTo150MHz = 11 + ] +], +USB0NEEDCLKCTRL [ + /// USB0 Device USB0_NEEDCLK signal control:. + AP_FS_DEV_NEEDCLK OFFSET(0) NUMBITS(1) [ + /// Under hardware control. + UnderHardwareControl = 0, + /// Forced high. + ForcedHigh = 1 + ], + /// USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + POL_FS_DEV_NEEDCLK OFFSET(1) NUMBITS(1) [ + /// Falling edge of device USB0_NEEDCLK triggers wake-up. + FallingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 0, + /// Rising edge of device USB0_NEEDCLK triggers wake-up. + RisingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 1 + ], + /// USB0 Host USB0_NEEDCLK signal control:. + AP_FS_HOST_NEEDCLK OFFSET(2) NUMBITS(1) [ + /// Under hardware control. + UnderHardwareControl = 0, + /// Forced high. + ForcedHigh = 1 + ], + /// USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + POL_FS_HOST_NEEDCLK OFFSET(3) NUMBITS(1) [ + /// Falling edge of device USB0_NEEDCLK triggers wake-up. + FallingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 0, + /// Rising edge of device USB0_NEEDCLK triggers wake-up. + RisingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 1 + ] +], +USB0NEEDCLKSTAT [ + /// USB0 Device USB0_NEEDCLK signal status:. + DEV_NEEDCLK OFFSET(0) NUMBITS(1) [ + /// USB0 Device clock is low. + USB0DeviceClockIsLow = 0, + /// USB0 Device clock is high. + USB0DeviceClockIsHigh = 1 + ], + /// USB0 Host USB0_NEEDCLK signal status:. + HOST_NEEDCLK OFFSET(1) NUMBITS(1) [ + /// USB0 Host clock is low. + USB0HostClockIsLow = 0, + /// USB0 Host clock is high. + USB0HostClockIsHigh = 1 + ] +], +FMCFLUSH [ + /// Flush control + FLUSH OFFSET(0) NUMBITS(1) [ + /// No action is performed. + NoActionIsPerformed = 0, + /// Flush the FMC buffer contents. + FlushTheFMCBufferContents = 1 + ] +], +MCLKIO [ + /// MCLK control. + MCLKIO OFFSET(0) NUMBITS(1) [ + /// input mode. + InputMode = 0, + /// output mode. + OutputMode = 1 + ] +], +USB1NEEDCLKCTRL [ + /// USB1 Device need_clock signal control: + AP_HS_DEV_NEEDCLK OFFSET(0) NUMBITS(1) [ + /// HOST_NEEDCLK is under hardware control. + HOST_NEEDCLKIsUnderHardwareControl = 0, + /// HOST_NEEDCLK is forced high. + HOST_NEEDCLKIsForcedHigh = 1 + ], + /// USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrup + POL_HS_DEV_NEEDCLK OFFSET(1) NUMBITS(1) [ + /// Falling edge of DEV_NEEDCLK triggers wake-up. + FallingEdgeOfDEV_NEEDCLKTriggersWakeUp = 0, + /// Rising edge of DEV_NEEDCLK triggers wake-up. + RisingEdgeOfDEV_NEEDCLKTriggersWakeUp = 1 + ], + /// USB1 Host need clock signal control: + AP_HS_HOST_NEEDCLK OFFSET(2) NUMBITS(1) [ + /// HOST_NEEDCLK is under hardware control. + HOST_NEEDCLKIsUnderHardwareControl = 0, + /// HOST_NEEDCLK is forced high. + HOST_NEEDCLKIsForcedHigh = 1 + ], + /// USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + POL_HS_HOST_NEEDCLK OFFSET(3) NUMBITS(1) [ + /// Falling edge of HOST_NEEDCLK triggers wake-up. + FallingEdgeOfHOST_NEEDCLKTriggersWakeUp = 0, + /// Rising edge of HOST_NEEDCLK triggers wake-up. + RisingEdgeOfHOST_NEEDCLKTriggersWakeUp = 1 + ], + /// Software override of device controller PHY wake up logic. + HS_DEV_WAKEUP_N OFFSET(4) NUMBITS(1) [ + /// Forces USB1_PHY to wake-up. + ForcesUSB1_PHYToWakeUp = 0, + /// Normal USB1_PHY behavior. + NormalUSB1_PHYBehavior = 1 + ] +], +USB1NEEDCLKSTAT [ + /// USB1 Device need_clock signal status:. + DEV_NEEDCLK OFFSET(0) NUMBITS(1) [ + /// DEV_NEEDCLK is low. + DEV_NEEDCLKIsLow = 0, + /// DEV_NEEDCLK is high. + DEV_NEEDCLKIsHigh = 1 + ], + /// USB1 Host need_clock signal status:. + HOST_NEEDCLK OFFSET(1) NUMBITS(1) [ + /// HOST_NEEDCLK is low. + HOST_NEEDCLKIsLow = 0, + /// HOST_NEEDCLK is high. + HOST_NEEDCLKIsHigh = 1 + ] +], +SDIOCLKCTRL [ + /// Programmable delay value by which cclk_in_drv is phase-shifted with regard to cc + CCLK_DRV_PHASE OFFSET(0) NUMBITS(2) [ + /// 0 degree shift. + _0DegreeShift = 0, + /// 90 degree shift. + _90DegreeShift = 1, + /// 180 degree shift. + _180DegreeShift = 2, + /// 270 degree shift. + _270DegreeShift = 3 + ], + /// Programmable delay value by which cclk_in_sample is delayed with regard to cclk_ + CCLK_SAMPLE_PHASE OFFSET(2) NUMBITS(2) [ + /// 0 degree shift. + _0DegreeShift = 0, + /// 90 degree shift. + _90DegreeShift = 1, + /// 180 degree shift. + _180DegreeShift = 2, + /// 270 degree shift. + _270DegreeShift = 3 + ], + /// Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + PHASE_ACTIVE OFFSET(7) NUMBITS(1) [ + /// Bypassed. + Bypassed = 0, + /// Activates phase shift logic. When active, the clock divider is active and phase + PH_SHIFT = 1 + ], + /// Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + CCLK_DRV_DELAY OFFSET(16) NUMBITS(5) [], + /// Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + CCLK_DRV_DELAY_ACTIVE OFFSET(23) NUMBITS(1) [ + /// Disable drive delay. + DisableDriveDelay = 0, + /// Enable drive delay. + EnableDriveDelay = 1 + ], + /// Programmable delay value by which cclk_in_sample is delayed with regard to cclk_ + CCLK_SAMPLE_DELAY OFFSET(24) NUMBITS(5) [], + /// Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + CCLK_SAMPLE_DELAY_ACTIVE OFFSET(31) NUMBITS(1) [ + /// Disables sample delay. + DisablesSampleDelay = 0, + /// Enables sample delay. + EnablesSampleDelay = 1 + ] +], +PLL1CTRL [ + /// Bandwidth select R value. + SELR OFFSET(0) NUMBITS(4) [], + /// Bandwidth select I value. + SELI OFFSET(4) NUMBITS(6) [], + /// Bandwidth select P value. + SELP OFFSET(10) NUMBITS(5) [], + /// Bypass PLL input clock is sent directly to the PLL output (default). + BYPASSPLL OFFSET(15) NUMBITS(1) [ + /// use PLL. + UsePLL = 0, + /// PLL input clock is sent directly to the PLL output. + PLLInputClockIsSentDirectlyToThePLLOutput = 1 + ], + /// bypass of the divide-by-2 divider in the post-divider. + BYPASSPOSTDIV2 OFFSET(16) NUMBITS(1) [ + /// use the divide-by-2 divider in the post-divider. + UseTheDivideBy2DividerInThePostDivider = 0, + /// bypass of the divide-by-2 divider in the post-divider. + BypassOfTheDivideBy2DividerInThePostDivider = 1 + ], + /// limup_off = 1 in spread spectrum and fractional PLL applications. + LIMUPOFF OFFSET(17) NUMBITS(1) [], + /// control of the bandwidth of the PLL. + BWDIRECT OFFSET(18) NUMBITS(1) [ + /// the bandwidth is changed synchronously with the feedback-divider. + TheBandwidthIsChangedSynchronouslyWithTheFeedbackDivider = 0, + /// modify the bandwidth of the PLL directly. + ModifyTheBandwidthOfThePLLDirectly = 1 + ], + /// bypass of the pre-divider. + BYPASSPREDIV OFFSET(19) NUMBITS(1) [ + /// use the pre-divider. + UseThePreDivider = 0, + /// bypass of the pre-divider. + BypassOfThePreDivider = 1 + ], + /// bypass of the post-divider. + BYPASSPOSTDIV OFFSET(20) NUMBITS(1) [ + /// use the post-divider. + UseThePostDivider = 0, + /// bypass of the post-divider. + BypassOfThePostDivider = 1 + ], + /// enable the output clock. + CLKEN OFFSET(21) NUMBITS(1) [ + /// Disable the output clock. + DisableTheOutputClock = 0, + /// Enable the output clock. + EnableTheOutputClock = 1 + ], + /// 1: free running mode. + FRMEN OFFSET(22) NUMBITS(1) [], + /// free running mode clockstable: Warning: Only make frm_clockstable = 1 after the + FRMCLKSTABLE OFFSET(23) NUMBITS(1) [], + /// Skew mode. + SKEWEN OFFSET(24) NUMBITS(1) [ + /// skewmode is disable. + SkewmodeIsDisable = 0, + /// skewmode is enable. + SkewmodeIsEnable = 1 + ] +], +PLL1STAT [ + /// lock detector output (active high) Warning: The lock signal is only reliable bet + LOCK OFFSET(0) NUMBITS(1) [], + /// pre-divider ratio change acknowledge. + PREDIVACK OFFSET(1) NUMBITS(1) [], + /// feedback divider ratio change acknowledge. + FEEDDIVACK OFFSET(2) NUMBITS(1) [], + /// post-divider ratio change acknowledge. + POSTDIVACK OFFSET(3) NUMBITS(1) [], + /// free running detector output (active high). + FRMDET OFFSET(4) NUMBITS(1) [] +], +PLL1NDEC [ + /// pre-divider divider ratio (N-divider). + NDIV OFFSET(0) NUMBITS(8) [], + /// pre-divider ratio change request. + NREQ OFFSET(8) NUMBITS(1) [] +], +PLL1MDEC [ + /// feedback divider divider ratio (M-divider). + MDIV OFFSET(0) NUMBITS(16) [], + /// feedback ratio change request. + MREQ OFFSET(16) NUMBITS(1) [] +], +PLL1PDEC [ + /// post-divider divider ratio (P-divider) + PDIV OFFSET(0) NUMBITS(5) [], + /// feedback ratio change request. + PREQ OFFSET(5) NUMBITS(1) [] +], +PLL0CTRL [ + /// Bandwidth select R value. + SELR OFFSET(0) NUMBITS(4) [], + /// Bandwidth select I value. + SELI OFFSET(4) NUMBITS(6) [], + /// Bandwidth select P value. + SELP OFFSET(10) NUMBITS(5) [], + /// Bypass PLL input clock is sent directly to the PLL output (default). + BYPASSPLL OFFSET(15) NUMBITS(1) [ + /// use PLL. + UsePLL = 0, + /// Bypass PLL input clock is sent directly to the PLL output. + BypassPLLInputClockIsSentDirectlyToThePLLOutput = 1 + ], + /// bypass of the divide-by-2 divider in the post-divider. + BYPASSPOSTDIV2 OFFSET(16) NUMBITS(1) [ + /// use the divide-by-2 divider in the post-divider. + UseTheDivideBy2DividerInThePostDivider = 0, + /// bypass of the divide-by-2 divider in the post-divider. + BypassOfTheDivideBy2DividerInThePostDivider = 1 + ], + /// limup_off = 1 in spread spectrum and fractional PLL applications. + LIMUPOFF OFFSET(17) NUMBITS(1) [], + /// Control of the bandwidth of the PLL. + BWDIRECT OFFSET(18) NUMBITS(1) [ + /// the bandwidth is changed synchronously with the feedback-divider. + TheBandwidthIsChangedSynchronouslyWithTheFeedbackDivider = 0, + /// modify the bandwidth of the PLL directly. + ModifyTheBandwidthOfThePLLDirectly = 1 + ], + /// bypass of the pre-divider. + BYPASSPREDIV OFFSET(19) NUMBITS(1) [ + /// use the pre-divider. + UseThePreDivider = 0, + /// bypass of the pre-divider. + BypassOfThePreDivider = 1 + ], + /// bypass of the post-divider. + BYPASSPOSTDIV OFFSET(20) NUMBITS(1) [ + /// use the post-divider. + UseThePostDivider = 0, + /// bypass of the post-divider. + BypassOfThePostDivider = 1 + ], + /// enable the output clock. + CLKEN OFFSET(21) NUMBITS(1) [ + /// disable the output clock. + DisableTheOutputClock = 0, + /// enable the output clock. + EnableTheOutputClock = 1 + ], + /// free running mode. + FRMEN OFFSET(22) NUMBITS(1) [ + /// free running mode is disable. + FreeRunningModeIsDisable = 0, + /// free running mode is enable. + FreeRunningModeIsEnable = 1 + ], + /// free running mode clockstable: Warning: Only make frm_clockstable =1 after the P + FRMCLKSTABLE OFFSET(23) NUMBITS(1) [], + /// skew mode. + SKEWEN OFFSET(24) NUMBITS(1) [ + /// skew mode is disable. + SkewModeIsDisable = 0, + /// skew mode is enable. + SkewModeIsEnable = 1 + ] +], +PLL0STAT [ + /// lock detector output (active high) Warning: The lock signal is only reliable bet + LOCK OFFSET(0) NUMBITS(1) [], + /// pre-divider ratio change acknowledge. + PREDIVACK OFFSET(1) NUMBITS(1) [], + /// feedback divider ratio change acknowledge. + FEEDDIVACK OFFSET(2) NUMBITS(1) [], + /// post-divider ratio change acknowledge. + POSTDIVACK OFFSET(3) NUMBITS(1) [], + /// free running detector output (active high). + FRMDET OFFSET(4) NUMBITS(1) [] +], +PLL0NDEC [ + /// pre-divider divider ratio (N-divider). + NDIV OFFSET(0) NUMBITS(8) [], + /// pre-divider ratio change request. + NREQ OFFSET(8) NUMBITS(1) [] +], +PLL0PDEC [ + /// post-divider divider ratio (P-divider) + PDIV OFFSET(0) NUMBITS(5) [], + /// feedback ratio change request. + PREQ OFFSET(5) NUMBITS(1) [] +], +PLL0SSCG0 [ + /// input word of the wrapper bit 31 to 0. + MD_LBS OFFSET(0) NUMBITS(32) [] +], +PLL0SSCG1 [ + /// input word of the wrapper bit 32. + MD_MBS OFFSET(0) NUMBITS(1) [], + /// md change request. + MD_REQ OFFSET(1) NUMBITS(1) [], + /// programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3 + MF OFFSET(2) NUMBITS(3) [], + /// programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[3 + MR OFFSET(5) NUMBITS(3) [], + /// modulation waveform control Compensation for low pass filtering of the PLL to ge + MC OFFSET(8) NUMBITS(2) [], + /// to select an external mdiv value. + MDIV_EXT OFFSET(10) NUMBITS(16) [], + /// to select an external mreq value. + MREQ OFFSET(26) NUMBITS(1) [], + /// dithering between two modulation frequencies in a random way or in a pseudo rand + DITHER OFFSET(27) NUMBITS(1) [], + /// to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = + SEL_EXT OFFSET(28) NUMBITS(1) [] +], +FUNCRETENTIONCTRL [ + /// functional retention in power down only. + FUNCRETENA OFFSET(0) NUMBITS(1) [ + /// disable functional retention. + DisableFunctionalRetention = 0, + /// enable functional retention. + EnableFunctionalRetention = 1 + ], + /// Start address divided by 4 inside SRAMX bank. + RET_START OFFSET(1) NUMBITS(13) [], + /// lenth of Scan chains to save. + RET_LENTH OFFSET(14) NUMBITS(10) [] +], +CPUCTRL [ + /// CPU1 clock enable. + CPU1CLKEN OFFSET(3) NUMBITS(1) [ + /// The CPU1 clock is not enabled. + TheCPU1ClockIsNotEnabled = 0, + /// The CPU1 clock is enabled. + TheCPU1ClockIsEnabled = 1 + ], + /// CPU1 reset. + CPU1RSTEN OFFSET(5) NUMBITS(1) [ + /// The CPU1 is not being reset. + TheCPU1IsNotBeingReset = 0, + /// The CPU1 is being reset. + TheCPU1IsBeingReset = 1 + ] +], +CPBOOT [ + /// Coprocessor Boot Address for CPU1. + CPBOOT OFFSET(0) NUMBITS(32) [] +], +CPSTAT [ + /// The CPU0 sleeping state. + CPU0SLEEPING OFFSET(0) NUMBITS(1) [ + /// the CPU is not sleeping. + TheCPUIsNotSleeping = 0, + /// the CPU is sleeping. + TheCPUIsSleeping = 1 + ], + /// The CPU1 sleeping state. + CPU1SLEEPING OFFSET(1) NUMBITS(1) [ + /// the CPU is not sleeping. + TheCPUIsNotSleeping = 0, + /// the CPU is sleeping. + TheCPUIsSleeping = 1 + ], + /// The CPU0 lockup state. + CPU0LOCKUP OFFSET(2) NUMBITS(1) [ + /// the CPU is not in lockup. + TheCPUIsNotInLockup = 0, + /// the CPU is in lockup. + TheCPUIsInLockup = 1 + ], + /// The CPU1 lockup state. + CPU1LOCKUP OFFSET(3) NUMBITS(1) [ + /// the CPU is not in lockup. + TheCPUIsNotInLockup = 0, + /// the CPU is in lockup. + TheCPUIsInLockup = 1 + ] +], +CLOCK_CTRL [ + /// Enable XTAL32MHz clock for Frequency Measure module. + XTAL32MHZ_FREQM_ENA OFFSET(1) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + FRO1MHZ_UTICK_ENA OFFSET(2) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable FRO 12MHz clock for Frequency Measure module. + FRO12MHZ_FREQM_ENA OFFSET(3) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable FRO 96MHz clock for Frequency Measure module. + FRO_HF_FREQM_ENA OFFSET(4) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable clock_in clock for clock module. + CLKIN_ENA OFFSET(5) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable FRO 1MHz clock for clock muxing in clock gen. + FRO1MHZ_CLK_ENA OFFSET(6) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable FRO 12MHz clock for analog control of the FRO 192MHz. + ANA_FRO12M_CLK_ENA OFFSET(7) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable clock for cristal oscilator calibration. + XO_CAL_CLK_ENA OFFSET(8) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ], + /// Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + PLU_DEGLITCH_CLK_ENA OFFSET(9) NUMBITS(1) [ + /// The clock is not enabled. + TheClockIsNotEnabled = 0, + /// The clock is enabled. + TheClockIsEnabled = 1 + ] +], +COMP_INT_CTRL [ + /// Analog Comparator interrupt enable control:. + INT_ENABLE OFFSET(0) NUMBITS(1) [ + /// interrupt disable. + InterruptDisable = 0, + /// interrupt enable. + InterruptEnable = 1 + ], + /// Analog Comparator interrupt clear. + INT_CLEAR OFFSET(1) NUMBITS(1) [ + /// No effect. + NoEffect = 0, + /// Clear the interrupt. Self-cleared bit. + ClearTheInterruptSelfClearedBit = 1 + ], + /// Comparator interrupt type selector:. + INT_CTRL OFFSET(2) NUMBITS(3) [ + /// The analog comparator interrupt edge sensitive is disabled. + TheAnalogComparatorInterruptEdgeSensitiveIsDisabled = 0, + /// The analog comparator interrupt level sensitive is disabled. + TheAnalogComparatorInterruptLevelSensitiveIsDisabled = 1, + /// analog comparator interrupt is rising edge sensitive. + AnalogComparatorInterruptIsRisingEdgeSensitive = 2, + /// Analog Comparator interrupt is high level sensitive. + AnalogComparatorInterruptIsHighLevelSensitive = 3, + /// analog comparator interrupt is falling edge sensitive. + AnalogComparatorInterruptIsFallingEdgeSensitive = 4, + /// Analog Comparator interrupt is low level sensitive. + AnalogComparatorInterruptIsLowLevelSensitive = 5, + /// analog comparator interrupt is rising and falling edge sensitive. + AnalogComparatorInterruptIsRisingAndFallingEdgeSensitive = 6 + ], + /// Select which Analog comparator output (filtered our un-filtered) is used for int + INT_SOURCE OFFSET(5) NUMBITS(1) [ + /// Select Analog Comparator filtered output as input for interrupt detection. + SelectAnalogComparatorFilteredOutputAsInputForInterruptDetection = 0, + /// Select Analog Comparator raw output (unfiltered) as input for interrupt detectio + RAW_INT = 1 + ] +], +COMP_INT_STATUS [ + /// Interrupt status BEFORE Interrupt Enable. + STATUS OFFSET(0) NUMBITS(1) [ + /// no interrupt pending. + NoInterruptPending = 0, + /// interrupt pending. + InterruptPending = 1 + ], + /// Interrupt status AFTER Interrupt Enable. + INT_STATUS OFFSET(1) NUMBITS(1) [ + /// no interrupt pending. + NoInterruptPending = 0, + /// interrupt pending. + InterruptPending = 1 + ], + /// comparator analog output. + VAL OFFSET(2) NUMBITS(1) [ + /// P+ is smaller than P-. + PIsSmallerThanP = 0, + /// P+ is greater than P-. + PIsGreaterThanP = 1 + ] +], +AUTOCLKGATEOVERRIDE [ + /// Control automatic clock gating of ROM controller. + ROM OFFSET(0) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAMX controller. + RAMX_CTRL OFFSET(1) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAM0 controller. + RAM0_CTRL OFFSET(2) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAM1 controller. + RAM1_CTRL OFFSET(3) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAM2 controller. + RAM2_CTRL OFFSET(4) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAM3 controller. + RAM3_CTRL OFFSET(5) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of RAM4 controller. + RAM4_CTRL OFFSET(6) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of synchronous bridge controller 0. + SYNC0_APB OFFSET(7) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of synchronous bridge controller 1. + SYNC1_APB OFFSET(8) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of CRCGEN controller. + CRCGEN OFFSET(11) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of DMA0 controller. + SDMA0 OFFSET(12) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of DMA1 controller. + SDMA1 OFFSET(13) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of USB controller. + USB0 OFFSET(14) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// Control automatic clock gating of synchronous system controller registers bank. + SYSCON OFFSET(15) NUMBITS(1) [ + /// Automatic clock gating is not overridden. + AutomaticClockGatingIsNotOverridden = 0, + /// Automatic clock gating is overridden (Clock gating is disabled). + AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1 + ], + /// The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields update + ENABLEUPDATE OFFSET(16) NUMBITS(16) [ + /// Bit Fields 0 - 15 of this register are not updated + BitFields015OfThisRegisterAreNotUpdated = 0, + /// Bit Fields 0 - 15 of this register are updated + BitFields015OfThisRegisterAreUpdated = 49374 + ] +], +GPIOPSYNC [ + /// Enable bypass of the first stage of synchonization inside GPIO_INT module. + PSYNC OFFSET(0) NUMBITS(1) [ + /// use the first stage of synchonization inside GPIO_INT module. + UseTheFirstStageOfSynchonizationInsideGPIO_INTModule = 0, + /// bypass of the first stage of synchonization inside GPIO_INT module. + BypassOfTheFirstStageOfSynchonizationInsideGPIO_INTModule = 1 + ] +], +DEBUG_LOCK_EN [ + /// Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITY + LOCK_ALL OFFSET(0) NUMBITS(4) [ + /// Any other value than b1010: disable write access to all 6 registers. + AnyOtherValueThanB1010DisableWriteAccessToAll6Registers = 0, + /// 1010: Enable write access to all 6 registers. + _1010EnableWriteAccessToAll6Registers = 10 + ] +], +DEBUG_FEATURES [ + /// CPU0 Invasive debug control:. + CPU0_DBGEN OFFSET(0) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Non Invasive debug control:. + CPU0_NIDEN OFFSET(2) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Secure Invasive debug control:. + CPU0_SPIDEN OFFSET(4) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Secure Non Invasive debug control:. + CPU0_SPNIDEN OFFSET(6) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU1 Invasive debug control:. + CPU1_DBGEN OFFSET(8) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU1 Non Invasive debug control:. + CPU1_NIDEN OFFSET(10) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ] +], +DEBUG_FEATURES_DP [ + /// CPU0 (CPU0) Invasive debug control:. + CPU0_DBGEN OFFSET(0) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Non Invasive debug control:. + CPU0_NIDEN OFFSET(2) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Secure Invasive debug control:. + CPU0_SPIDEN OFFSET(4) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU0 Secure Non Invasive debug control:. + CPU0_SPNIDEN OFFSET(6) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU1 Invasive debug control:. + CPU1_DBGEN OFFSET(8) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ], + /// CPU1 Non Invasive debug control:. + CPU1_NIDEN OFFSET(10) NUMBITS(2) [ + /// Any other value than b10: invasive debug is disable. + AnyOtherValueThanB10InvasiveDebugIsDisable = 1, + /// 10: Invasive debug is enabled. + _10InvasiveDebugIsEnabled = 2 + ] +], +KEY_BLOCK [ + /// Write a value to block quiddikey/PUF all index. + KEY_BLOCK OFFSET(0) NUMBITS(32) [] +], +DEBUG_AUTH_BEACON [ + /// Set by the debug authentication code in ROM to pass the debug beacons (Credentia + BEACON OFFSET(0) NUMBITS(32) [] +], +CPUCFG [ + /// Enable CPU1. + CPU1ENABLE OFFSET(2) NUMBITS(1) [ + /// CPU1 is disable (Processor in reset). + CPU1IsDisableProcessorInReset = 0, + /// CPU1 is enable. + CPU1IsEnable = 1 + ] +], +DEVICE_ID0 [ + /// ROM revision. + ROM_REV_MINOR OFFSET(20) NUMBITS(4) [] +], +DIEID [ + /// Chip Metal Revision ID. + REV_ID OFFSET(0) NUMBITS(4) [], + /// Chip Number 0x426B. + MCO_NUM_IN_DIE_ID OFFSET(4) NUMBITS(20) [] +], +PRESETCTRLSET0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRLSET1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRLSET2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRLCLR0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRLCLR1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +PRESETCTRLCLR2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +pub AHBCLKCTRLSET0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRLSET1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRLSET2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRLCLR0 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRLCLR1 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +], +AHBCLKCTRLCLR2 [ + /// Data array value + DATA OFFSET(0) NUMBITS(32) [] +] +]; +pub const SYSCON_BASE: StaticRef = + unsafe { StaticRef::new(0x40000000 as *const SysconRegisters) }; From 3c7818fdd03c0bbd9aae8cf6d51e2733873b6f4c Mon Sep 17 00:00:00 2001 From: user3345 <81963672+genan2003@users.noreply.github.com> Date: Tue, 16 Sep 2025 16:19:43 +0300 Subject: [PATCH 2/2] feat: Add LPC55 support files and core modifications Signed-off-by: user3345 <81963672+genan2003@users.noreply.github.com> --- Cargo.toml | 2 + chips/Cargo.toml | 339 ----------------------------------------------- 2 files changed, 2 insertions(+), 339 deletions(-) delete mode 100644 chips/Cargo.toml diff --git a/Cargo.toml b/Cargo.toml index fe9d1363e7..0799f9b8c0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -27,6 +27,7 @@ members = [ "boards/hifive1", "boards/imix", "boards/imxrt1050-evkb", + "boards/lpc55s69-evk", "boards/litex/arty", "boards/litex/sim", "boards/msp_exp432p401r", @@ -81,6 +82,7 @@ members = [ "chips/esp32", "chips/esp32-c3", "chips/imxrt10xx", + "chips/lpc55s6x", "chips/litex", "chips/litex_vexriscv", "chips/lowrisc", diff --git a/chips/Cargo.toml b/chips/Cargo.toml deleted file mode 100644 index 0799f9b8c0..0000000000 --- a/chips/Cargo.toml +++ /dev/null @@ -1,339 +0,0 @@ -# Licensed under the Apache License, Version 2.0 or the MIT License. -# SPDX-License-Identifier: Apache-2.0 OR MIT -# Copyright Tock Contributors 2022. - -[workspace] -members = [ - "arch/cortex-m", - "arch/cortex-v7m", - "arch/cortex-m0", - "arch/cortex-m0p", - "arch/cortex-m3", - "arch/cortex-m33", - "arch/cortex-m4", - "arch/cortex-m7", - "arch/riscv", - "arch/rv32i", - "arch/x86", - "boards/nano_rp2040_connect", - "boards/arty_e21", - "boards/opentitan/earlgrey-cw310", - "boards/esp32-c3-devkitM-1", - "boards/cy8cproto_62_4343_w", - "boards/clue_nrf52840", - "boards/veer_el2_sim", - "boards/hail", - "boards/hifive_inventor", - "boards/hifive1", - "boards/imix", - "boards/imxrt1050-evkb", - "boards/lpc55s69-evk", - "boards/litex/arty", - "boards/litex/sim", - "boards/msp_exp432p401r", - "boards/microbit_v2", - "boards/wm1110dev", - "boards/makepython-nrf52840", - "boards/nordic/nrf52840dk", - "boards/nordic/nrf52840_dongle", - "boards/nordic/nrf52dk", - "boards/sma_q3", - "boards/nucleo_f429zi", - "boards/nucleo_f446re", - "boards/particle_boron", - "boards/pico_explorer_base", - "boards/raspberry_pi_pico", - "boards/raspberry_pi_pico_2", - "boards/apollo3/redboard_artemis_atp", - "boards/apollo3/redboard_artemis_nano", - "boards/apollo3/lora_things_plus", - "boards/redboard_redv", - "boards/stm32f3discovery", - "boards/stm32f412gdiscovery", - "boards/stm32f429idiscovery", - "boards/teensy40", - "boards/nano33ble", - "boards/nano33ble_rev2", - "boards/qemu_i486_q35", - "boards/qemu_rv32_virt", - "boards/weact_f401ccu6/", - "boards/configurations/nrf52840dk/nrf52840dk-test-appid-ecdsap256", - "boards/configurations/nrf52840dk/nrf52840dk-test-appid-sha256", - "boards/configurations/nrf52840dk/nrf52840dk-test-appid-tbf", - "boards/configurations/nrf52840dk/nrf52840dk-test-invs", - "boards/configurations/nrf52840dk/nrf52840dk-test-kernel", - "boards/configurations/nrf52840dk/nrf52840dk-test-dynamic-app-load", - "boards/configurations/microbit_v2/microbit_v2-test-dynamic-app-load", - "boards/tutorials/nrf52840dk-root-of-trust-tutorial", - "boards/tutorials/nrf52840dk-dynamic-apps-and-policies", - "boards/tutorials/nrf52840dk-hotp-tutorial", - "boards/tutorials/nrf52840dk-thread-tutorial", - "capsules/aes_gcm", - "capsules/ecdsa_sw", - "capsules/core", - "capsules/extra", - "capsules/system", - "chips/apollo3", - "chips/arty_e21_chip", - "chips/e310_g002", - "chips/e310_g003", - "chips/e310x", - "chips/earlgrey", - "chips/esp32", - "chips/esp32-c3", - "chips/imxrt10xx", - "chips/lpc55s6x", - "chips/litex", - "chips/litex_vexriscv", - "chips/lowrisc", - "chips/msp432", - "chips/nrf52", - "chips/nrf52832", - "chips/nrf52833", - "chips/nrf52840", - "chips/nrf5x", - "chips/x86_q35", - "chips/qemu_rv32_virt_chip", - "chips/psoc62xa", - "chips/rp2040", - "chips/rp2350", - "chips/sam4l", - "chips/segger", - "chips/sifive", - "chips/stm32f303xc", - "chips/stm32f401cc", - "chips/stm32f429zi", - "chips/stm32f446re", - "chips/stm32f412g", - "chips/stm32f4xx", - "chips/veer_el2", - "chips/virtio", - "kernel", - "libraries/enum_primitive", - "libraries/riscv-csr", - "libraries/tock-cells", - "libraries/tock-register-interface", - "libraries/tickv", -] -exclude = ["tools/"] -resolver = "2" - -[workspace.package] -version = "0.2.3-dev" -authors = ["Tock Project Developers "] -edition = "2021" - -[profile.dev] -panic = "abort" -lto = true -opt-level = "z" -debug = true - -[profile.release] -panic = "abort" -lto = true -opt-level = "z" -debug = true -codegen-units = 1 - -# CLIPPY CONFIGURATION -# -# We first disallow all lints in a particular group, then re-allow each one -# Tock does not comply with or we do not want to use. -# -# For each group there are three sections: -# 1. The first section are lints we don't want with a comment explaining our use -# case for not enabling that lint. -# 2. The second section are lints we may not want, we probably have to see the -# resulting diff. -# 3. The third section are lints that we do want we just need to fixup the code -# to pass the lint checks. -[workspace.lints.clippy] -# RESTRICTION LINTS -restriction = { level = "allow", priority = -1 } -unused_result_ok = "deny" - -# COMPLEXITY LINTS -complexity = { level = "deny", priority = -1 } - -# Subjective, and complex functions may need many arguments. -too_many_arguments = "allow" -# This is pretty sensitive, even `Result`s with returned buffers trigger this. -# It is not worth us creating types for all of these. -type_complexity = "allow" -# We use options extensively and they can be as clear as if let statements. -option_map_unit_fn = "allow" -# Sometimes the semantic meaning of variables means it is more clear to use -# nonminimal if statements, particularly when matching hardware or datasheets. -nonminimal_bool = "allow" -# Particularly for setting register values, expressing a zero offset can be -# semantically meaningful and encourage consistency between several lines of -# code. -identity-op = "allow" -# Subjective, and for SyscallDrivers sometimes enumerating the specific command -# numbers rather than using a range is semantically more clear. -manual-range-patterns = "allow" -# Particularly when interactive with hardware, including a leading zero can -# often be semantically more clear. -zero_prefixed_literal = "allow" - - -manual-flatten = "allow" - - -# STYLE -style = { level = "deny", priority = -1 } - -# Sometimes an if block is standalone and shouldn't be merged with an else. -collapsible_else_if = "allow" -# Multiple if blocks can be clearer to express a particular logical flow. -collapsible_if = "allow" -# Sometimes if statements are easier to read than match statements. -comparison_chain = "allow" -# Sometimes it's more clear to have repetition in enum names. -enum-variant-names = "allow" -# For buffers, `.get(0)` (using byte index) makes more sense than `.first()`. -get_first = "allow" -# There are often good reasons to enumerate different states that have the same -# effect. -if_same_then_else = "allow" -# Buffers and objects can have a length of 0, but it isn't necessarily intuitive -# to think of a buffer or those objects as "empty". -len_without_is_empty = "allow" -# Buffer logic often makes more sense with lengths, and not `is_empty()`. -len_zero = "allow" -# Sometimes the borrow checker works better with `match` instead of `.map()`. -manual-map = "allow" -# Syntax like `!(-17..=4).contains(&x)` is just not clear. -manual_range_contains = "allow" -# Match statement is clear, using `matches!()` is not an improvement. -match_like_matches_macro = "allow" -# Sometimes it makes sense to have module in a folder of the same name. -module_inception = "allow" -# Maybe someday we want this, but right now `for i in 0..4` is much more clear -# than using `.iter()` functions like `.skip(n)`. -needless-range-loop = "allow" -# We don't need unused Default implementations. -new_without_default = "allow" -# Using `Result()` is good practice, even if there is no meaning to the error. -result_unit_err = "allow" -# For hardware registers it can make sense to group bits semantically and not -# just in multiples of four. -unusual-byte-groupings = "allow" -# We widely use upper case acronyms for hardware registers and fields. -upper_case_acronyms = "allow" - - -missing_safety_doc = "allow" -doc_lazy_continuation = "allow" - - -# PERF -perf = { level = "deny", priority = -1 } - -# Tock extensively uses enums for state machines, and it often is much clearer -# to store objects between states in the state enum rather than as "global" -# variables in the struct itself. Therefore, some enums end up quite large. -large-enum-variant = "allow" - - -# CARGO -cargo = { level = "deny", priority = -1 } - -# Tock includes over 100 crates, and it is just too pedantic to expect each one -# to have full and correct metadata. -cargo_common_metadata = "allow" -# We generally avoid all cargo features, and therefore it isn't intuitive that -# we would expect some features to be enabled by default, so it can make sense -# to have a feature to disable something. -negative-feature-names = "allow" - - -# NURSERY -nursery = { level = "deny", priority = -1 } - -# In some cases we mark `pub(crate)` in a module which isn't exposed outside of -# the crate. This redundancy is OK, and if the module were to be made public -# for some reason in the future the visibility would transparently change. -redundant_pub_crate = "allow" -# Sometimes a `map_or_else()` seems like a better option, but it doesn't always -# pass the borrow checker. if let/else is more reliable. -option_if_let_else = "allow" -# Some OS functions are necessarily complex. -cognitive_complexity = "allow" - - -unused_peekable = "allow" -branches_sharing_code = "allow" - - -use_self = "allow" -or_fun_call = "allow" -missing_const_for_fn = "allow" -equatable_if_let = "allow" -derive_partial_eq_without_eq = "allow" -empty_line_after_doc_comments = "allow" -trait_duplication_in_bounds = "allow" -useless_let_if_seq = "allow" - - -# PEDANTIC -pedantic = { level = "deny", priority = -1 } - -doc_markdown = "allow" -missing_errors_doc = "allow" -if_not_else = "allow" -cast_sign_loss = "allow" -too_many_lines = "allow" -must_use_candidate = "allow" -manual_let_else = "allow" -single_match_else = "allow" -inline_always = "allow" -module_name_repetitions = "allow" -unnested-or-patterns = "allow" -redundant_else = "allow" -return_self_not_must_use = "allow" -match_same_arms = "allow" -explicit_iter_loop = "allow" -similar_names = "allow" -unnecessary_wraps = "allow" -manual_assert = "allow" -transmute_ptr_to_ptr = "allow" -struct_excessive_bools = "allow" -fn_params_excessive_bools = "allow" -trivially_copy_pass_by_ref = "allow" -borrow_as_ptr = "allow" -tuple_array_conversions = "allow" -verbose_bit_mask = "allow" -large_types_passed_by_value = "allow" -no_mangle_with_rust_abi = "allow" -struct_field_names = "allow" -needless_continue = "allow" - - -cast_lossless = "allow" -cast_possible_truncation = "allow" -cast_precision_loss = "allow" -range_plus_one = "allow" -missing_panics_doc = "allow" -match_wildcard_for_single_variants = "allow" -unused_self = "allow" -cast-possible-wrap = "allow" -uninlined_format_args = "allow" -unreadable_literal = "allow" -needless_pass_by_value = "allow" -items_after_statements = "allow" -ref_option_ref = "allow" -match_bool = "allow" -redundant_closure_for_method_calls = "allow" -no_effect_underscore_binding = "allow" -iter_without_into_iter = "allow" - - -semicolon_if_nothing_returned = "allow" -ptr_as_ptr = "allow" -ptr_cast_constness = "allow" -mut_mut = "allow" -cast_ptr_alignment = "allow" -used_underscore_binding = "allow" -checked_conversions = "allow"