How should I use picker to test clock domain crossing circuits?

[Devil-SX]

[yaozhicheng]

You can refer to the implementation of xclock and implement dual-clock or multi-clock management on your own. Contributions of Pull requests (PRs) are also welcome.

[Makiras]

It is preferable to implement the different clocks on the Verilog side, although support is also available on the Python side. In a multi-clock scenario, each Step() should be considered as one minimal timeframe (such as 1ps). You can manually process the clock edge for each different clock.

For example,Clock A 3ps /cycle and Clock B 5ps /cycle, start with 0

Time (ps)	0	3	5	6	9	10	12	15
Clock	-	A+	B+	A-	A+	B-	A-	A+, B+
Step() Count	0	3	5	6	9	10	12	15

The toffe clock does not yet support cross clock-zone functionality, so you will need to handle it manually. If you have any questions, feel free to ask.

[Makiras]

In the future, we plan to enhance our support for multi-clock such as configurable mutli-clock witch auto match for toffe. If you have any suggestions, they would be greatly appreciated.

[yaozhicheng]

@Devil-SX XClock has added a frequency division feature, which can be used to implement multi-clocks. You can refer to MultiClock for an example.