Other input for RapidWright for logical netlist rather than EDIF format

[coherent17]

Hi RapidWright team,

I'm curious whether RapidWright provides a way for users to register custom parsers so they can parse their own netlist formats into the RapidWright database for logical netlist.

Currently, to parse an EDIF netlist, I use RapidWright's ParallelEDIFParser. Is there a way to have something like a ParallelCustomNetlistParser that would allow users to parse their own netlist formats? Since our design is relatively large (>90% utilization on a Versal [xcvp1902] FPGA), converting from our original format to EDIF takes significant time and disk space.

Thanks!
Coherent

[clavin-xlnx]

Hi Coherent,

This is an interesting idea, although, we don't currently have a "parser registration" process currently. One could envision that we could also support structural Verilog in this way.

One of the big considerations is supporting parallelism. The parallel EDIF parser is fine tuned for the structure of EDIF and another format may need to adapt in a different way.

Is the file format support you hope to add one that you can share?