Added clock connection to shift reg.

Signed-off-by: Alexandru Ulmamei <alexandru.ulmamei@upb.ro>

Author: hpc-aulmamei

linker/resources/service_layer.tcl

@@ -1070,7 +1070,8 @@ update_compile_order -fileset sources_1
   [get_bd_pins axi_register_slice_8/aclk] \
   [get_bd_pins noc_virt_3/aclk0] \
   [get_bd_pins noc_virt_2/aclk0] \
-  [get_bd_pins noc_virt_4/aclk0] 
+  [get_bd_pins noc_virt_4/aclk0] \
+  [get_bd_pins c_shift_ram_0/CLK]
 
   connect_bd_net -net proc_sys_reset_0_peripheral_aresetn  [get_bd_pins ilreduced_logic_0/Res] \
   [get_bd_pins axi4_full_passthrough_0/aresetn] \

linker/resources/slash.tcl

@@ -960,7 +960,8 @@ update_compile_order -fileset sources_1
   [get_bd_pins noc_virt_02/aclk0] \
   [get_bd_pins noc_virt_03/aclk0] \
   [get_bd_pins qdma_slave_bridge_noc/aclk0] \
-  [get_bd_pins axi_noc_0/aclk0]
+  [get_bd_pins axi_noc_0/aclk0] \
+  [get_bd_pins c_shift_ram_0/CLK]
 
 
   connect_bd_net -net xlconstant_0_dout  [get_bd_pins xlconstant_0/dout] \