15-post-link-recompile

AMD Vitis™ AI Engine Tutorials See Vitis Development Environment on amd.com See Vitis AI Development Environment on amd.com

Post-Link Recompile of an AI Engine Application

Version: Vitis 2025.2

Introduction

AI Engine application development can start early in the system development stage. AMD Versal™ adaptive SoCs combine programmable logic (PL), processing systems (PS), and AI Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. A host of tools, software, libraries, IP, middleware, and frameworks enable Versal adaptive SoCs to support all industry-standard design flows.

This tutorial shows you how to modify an AI Engine application after the platform freezes while avoiding a complete AMD Vivado™ tool run, which can take long if timing closure requires specific attention.

There are two ways to perform this operation:

1. Recompile the AI Engine application right after the link stage, using specific constraints to set the interface ports.
2. Use the output .xsa file as a platform, which embeds these constraints.

In the first case, you have to remove the constraints from the files generated by the AI Engine compiler and use them as input constraints when you run it for the second time.

In the second case, you use the .xsa file generated during the link stage as the target platform, which contains the constraints already on the AI Engine array interface specification. This tutorial explains the complete flow for these two cases.

This tutorial details all the steps to perform hardware emulation (hw_emu), but it also supports the hardware implementation flow by changing the compilation target.

IMPORTANT: Before beginning the tutorial, make sure that you have installed the Vitis 2025.2 software. The Vitis release includes all the embedded base platforms including the VCK190 base platform that this tutorial uses. Download the Common Images for Embedded Vitis Platforms from this link https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms/2025.2.html. The ‘common image’ package contains a prebuilt Linux kernel and root file system that you can use with the Versal board for embedded design development using Vitis. Before starting this tutorial, run the following steps:

1. Go to the directory where you have unzipped the Versal Common Image package.
2. In a Bash shell, run the /Common Images Dir/xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linux script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, run the /Common Images Dir/xilinx-versal-common-v2025.2/sdk.sh.
3. Set up your ROOTFS, and IMAGE to point to the rootfs.ext4 and Image files located in the /Common Images Dir/xilinx-versal-common-v2025.2 directory.
4. Set up your PLATFORM_REPO_PATHS environment variable to $XILINX_VITIS/base_platforms/.

This tutorial targets the VCK190 production board for 2025.2 version.

The sub-directory Files contains all the source files necessary for this tutorial.

AI Engine Application Post-Link Recompile

This tutorial contains the following labs:

• Lab 1 uses a direct recompile Makefile flow.
• Lab 2 uses a Vitis Makefile flow.

Each lab has the following phases:

1. Creating an AI Engine application using the VCK190 platform with all necessary PL kernels added, and linking the complete system.
2. Creating a new AI Engine application with interface location constraints (Lab 1) or with the previously created fixed platform (Lab 2), adding a PS application, and running hardware emulation.

Objectives

This tutorial shows you how to modify an AI Engine application after the platform freezes. It demonstrates a Vitis Makefile flow.

When you complete this tutorial you can confidently develop AI Engine designs based on a hardware or software platform, knowing that you can modify the AI Engine part and the processing system control application. The only limitation is that the hardware connection between the AI Engine array and the PL must stay fixed.

License

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The MIT License (MIT)

Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: MIT

Support

GitHub issues track requests and bugs. For questions, go to support.xilinx.com.

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