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Lab 3: Timing and Resource Analysis

In this lab, you learn how to verify the functionality of your designs by simulating in Simulink® to ensure that your Vitis Model Composer design is correct when you implement the design in your target AMD device.

Objectives

After completing this lab, you will be able to:

  • Identify timing issues in the HDL files generated by Vitis Model Composer and discover the source of the timing violations in your design.
  • Perform resource analysis and access the existing resource analysis results, along with recommendations to optimize.

Procedure

This lab has two primary parts:

  • In Step 1 you will learn how to do timing analysis in Vitis Model Composer.
  • In Step 2 you will learn how to perform resource analysis in Vitis Model Composer.

Step 1: Timing Analysis in Vitis Model Composer

  1. Invoke Vitis Model Composer.

    • On Windows systems select Windows > AMD Design Tools > Vitis Model Composer 2025.2.
    • On Linux systems, type model_composer at the command prompt.

  2. Navigate to the Lab3 folder: \HDL_Library\Lab3.

You can view the directory contents in the MATLAB® Current Folder browser, or type ls at the command line prompt.

  1. Open the Lab3 design using one of the following:
    • At the MATLAB command prompt, type open Lab3.slx
    • Double-click Lab3.slx in the Current Folder browser.

The Lab3 design opens, as shown in the following figure.

Note that this design differs from the previous labs in that all of the HDL blocks are placed inside a subsystem (HDL_DUT) while the Vitis Model Composer Hub block remains at the top level of the model. Going forward, this is a recommended approach for architecting your model using Vitis Model Composer.

  1. From the Simulink Toolstrip, click the Run button to simulate the design.

  2. Double-click the Vitis Model Composer Hub block to open the Properties Editor.

  3. Select the HDL_DUT subsystem on the left, then the Analyze tab.

  4. From the Perform Analysis menu, select Post Synthesis and from Analyzer type menu select Timing as shown in the following figure.

  1. In the Model Composer Hub dialog box, click Analyze.

When you generate, the following occurs:

  • Vitis Model Composer generates the required files for the selected compilation target. For timing analysis Vitis Model Composer invokes Vivado in the background for the design project, and passes design timing constraints to Vivado.
  • Depending on your selection for Perform Analysis (Post Synthesis or Post Implementation), the design runs in Vivado through synthesis or through implementation.
  • After the Vivado tools run is completed, timing paths information is collected and saved in a specific file format from the Vivado timing database.
  • Vitis Model Composer processes the timing information and displays a Timing Analyzer table with timing paths information as shown in the following figure.

In the timing analyzer table, paths with lowest slack values display, with the worst slack showing at the top and increasing toward the bottom. Paths with timing violations have a negative slack and display in red.

  1. Cross probe from the Timing Analyzer table to the Simulink model by clicking any path in the Timing Analyzer table, which highlights the corresponding Vitis Model Composer HDL blocks in the model. This allows you to troubleshoot timing violations by analyzing the path on which they occur.

When you cross probe, you see the corresponding path as shown in the following figure. Blocks with timing violations are highlighted in red.

  1. Double-click the second path in the Timing Analyzer table and cross-probe, the corresponding highlighted path in green which indicates no timing violation.

If you close the Timing Analyzer sometime later you might want to relaunch the Timing Analyzer table using the existing timing analyzer results for the model. To do this, simply click Analyze in the Model Composer Hub block again. The table that opens will display the results stored in the Target Directory specified in the Model Composer Hub dialog box, regardless of the option selected for Perform Analysis (Post Synthesis or Post Implementation).

Troubleshooting Timing Violations

Inserting some registers in the combinational path might give better timing results and might help overcome timing violations if any. This can be done by changing latency of the combinational blocks as explained in the following.

  1. Click the violated path from the Timing Analyzer window which opens the violated path.

  2. Double-click the coef block to open the Single Port RAM block parameters window as shown in the following figure.

  1. Under Basic tab, change the latency from 1 to 2 and click OK.

  2. Double-click the Model Composer Hub block, ensure that the Analysis Type is Timing and click Analyze.

After the generation completes, it opens the timing Analyzer table as shown in the following figure. Observe the status pass at the top-right corner. It indicates there are no timing violated paths in the design.

📝 Note: a. For quicker timing analysis iterations, post-synthesis analysis is preferred over post-implementation analysis. b. Changing the latency of the block might increase the number of resources which can be seen using Step 2: Resource Analysis in Vitis Model Composer.

Step 2: Resource Analysis in Vitis Model Composer

In this step we use same design, Lab3.slx, used for Step 1 but we are going to perform Resource Analysis.

⭐ Tip: Resource Analysis can be performed whenever you generate any of the following export types:

  • IP catalog
  • Hardware Co-Simulation
  • Synthesized Checkpoint
  • HDL Netlist
  1. Double-click the Model Composer Hub block in the Simulink model. On the Export tab, ensure that one of the Export Types listed above is selected.

  1. In the Analyze tab, set the Perform Analysis field to Post Synthesis and Analysis Type type field to Resource.

📝 Note: In order to see accurate results from Resource Analyzer Window it is recommended to specify a new target directory rather than use the current working directory.

  1. In the Model Composer Hub dialog box, click Analyze.

Model Composer processes the resource utilization data and displays a Resource Analyzer window with resource utilization information.

Each column heading (for example, BRAMs, DSPs, or LUTs) in the window shows the total number of each type of resources available in the AMD device for which you are targeting your design. The rest of the window displays a hierarchical listing of each subsystem and block in the design, with the count of these resource types.

You can cross probe from the Resource Analyzer window to the Simulink model by clicking a block or subsystem name in the Resource Analyzer window, which highlights the corresponding Vitis Model Composer HDL block or subsystem in the model.

Cross probing is useful to identify blocks and subsystems that are implemented using a particular type of resource. The block you have selected in the window will be highlighted yellow and outlined in red. If the block or subsystem you have selected in the window is within an upper-level subsystem, then the parent subsystem is highlighted in red in addition to the underlying block as shown in the following figure.

❗❗ Important: If the Resource Analyzer window or the Timing Analyzer window opens and no information is displayed in the window (table cells are empty), double-click the Model Composer Hub block and set the Target Directory to a new directory, that is, a directory that has not been used before. Then run the analysis again.

Summary

In this lab you learned how to use timing and resource analysis inside Model Composer which, in turn, invokes Vivado synthesis to collect the information for the analysis. You also learned how to identify timing violated paths and to troubleshoot them for simple designs.

Copyright (c) 2025 Advanced Micro Devices, Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.