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QDMA DPDK reference driver for v2023.1.2 release
1 parent 3414e26 commit 0e8d321

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10 files changed

+952
-348
lines changed

10 files changed

+952
-348
lines changed

‎QDMA/DPDK/RELEASE‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
RELEASE: 2023.1.1
1+
RELEASE: 2023.1.2
22
=================
33

44
This release is based on DPDK v20.11, v21.11 and v22.11 and
@@ -121,14 +121,17 @@ CPM5
121121
----------------
122122
- Optimized the driver code and HW register settings for performance improvements
123123

124+
2023.1.2 Updates
125+
----------------
126+
- Optimized dpdk PMD and HW register settings for CPM5 performance improvements
127+
124128
KNOWN ISSUE:
125129
============
126130
- CPM5:
127-
- Performance optimizations are not finalized, Updated Performance report with some more optimizations will be available in next patch release.
131+
- Smaller packet forwarding performance optimizations are in progress and report will be updated in subsequent releases
128132

129133
- All Designs
130134
- Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
131-
- DPDK C2H and Forwarding performance values for 8 queue is lesser compared to 4 queue case for both PF and VF.
132135

133136

134137
DRIVER LIMITATIONS:
@@ -139,7 +142,6 @@ DRIVER LIMITATIONS:
139142
- All Designs
140143
- Big endian systems are not supported
141144
- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
142-
- Current 2023.1.0 driver which is supporting DPDK 22.11/21.11 is not fully verified for stress, multicard, tandem boot and interop use cases. These will be verified and confirmed in next patch release.
143145

144146

145147
/*-

‎QDMA/DPDK/drivers/net/qdma/meson.build‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,6 @@ cflags += ['-DRTE_LIBRTE_QDMA_PMD']
3333
cflags += ['-DDMA_BRAM_SIZE=524288']
3434
cflags += ['-DTHROUGHPUT_MEASUREMENT']
3535

36-
# Enable vectorization in qdma data path to use 128-bit SIMD registers
37-
cflags += ['-DQDMA_RX_VEC_X86_64']
38-
cflags += ['-DQDMA_TX_VEC_X86_64']
39-
4036
# Use QDMA_DPDK_22_11 compiler flag for DPDK v22.11
4137
# Use QDMA_DPDK_21_11 compiler flag for DPDK v21.11
4238
# Use QDMA_DPDK_20_11 compiler flag for DPDK v20.11
@@ -77,3 +73,7 @@ sources = files(
7773
'rte_pmd_qdma.c',
7874
'qdma_dpdk_compat.c'
7975
)
76+
77+
if arch_subdir == 'x86'
78+
sources += files('qdma_rxtx_vec_sse.c')
79+
endif

‎QDMA/DPDK/drivers/net/qdma/qdma.h‎

Lines changed: 35 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -345,6 +345,9 @@ struct qdma_pci_dev {
345345

346346
int16_t tx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
347347
int16_t rx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
348+
349+
uint8_t rx_vec_allowed:1;
350+
uint8_t tx_vec_allowed:1;
348351
};
349352

350353
void qdma_dev_ops_init(struct rte_eth_dev *dev);
@@ -376,15 +379,20 @@ int qdma_identify_bars(struct rte_eth_dev *dev);
376379
int qdma_get_hw_version(struct rte_eth_dev *dev);
377380

378381
/* implemented in rxtx.c */
379-
uint16_t qdma_recv_pkts_st(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts,
382+
uint16_t qdma_recv_pkts_st(void *rx_queue, struct rte_mbuf **rx_pkts,
380383
uint16_t nb_pkts);
381-
uint16_t qdma_recv_pkts_mm(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts,
384+
uint16_t qdma_recv_pkts_mm(void *rx_queue, struct rte_mbuf **rx_pkts,
382385
uint16_t nb_pkts);
383-
uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
386+
uint16_t qdma_xmit_pkts_st(void *tx_queue, struct rte_mbuf **tx_pkts,
384387
uint16_t nb_pkts);
385-
uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
388+
uint16_t qdma_xmit_pkts_mm(void *tx_queue, struct rte_mbuf **tx_pkts,
386389
uint16_t nb_pkts);
387390

391+
#ifdef TEST_64B_DESC_BYPASS
392+
uint16_t qdma_xmit_64B_desc_bypass(struct qdma_tx_queue *txq,
393+
struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
394+
#endif
395+
388396
uint32_t qdma_pci_read_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg);
389397
void qdma_pci_write_reg(struct rte_eth_dev *dev, uint32_t bar,
390398
uint32_t reg, uint32_t val);
@@ -414,4 +422,27 @@ bool is_vf_device_supported(struct rte_eth_dev *dev);
414422
bool is_pf_device_supported(struct rte_eth_dev *dev);
415423

416424
void qdma_check_errors(void *arg);
425+
426+
struct rte_mbuf *prepare_segmented_packet(struct qdma_rx_queue *rxq,
427+
uint16_t pkt_length, uint16_t *tail);
428+
int reclaim_tx_mbuf(struct qdma_tx_queue *txq,
429+
uint16_t cidx, uint16_t free_cnt);
430+
int qdma_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info);
431+
int qdma_ul_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info);
432+
433+
/* Transmit API for Streaming mode */
434+
uint16_t qdma_xmit_pkts_vec(void *tx_queue,
435+
struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
436+
uint16_t qdma_xmit_pkts_st_vec(void *tx_queue,
437+
struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
438+
439+
/* Receive API for Streaming mode */
440+
uint16_t qdma_recv_pkts_vec(void *rx_queue,
441+
struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
442+
uint16_t qdma_recv_pkts_st_vec(void *rx_queue,
443+
struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
444+
445+
void __rte_cold qdma_set_tx_function(struct rte_eth_dev *dev);
446+
void __rte_cold qdma_set_rx_function(struct rte_eth_dev *dev);
447+
417448
#endif /* ifndef __QDMA_H__ */

‎QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,9 @@
9999
#define EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK BIT(1)
100100
#define EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK BIT(0)
101101

102-
#define EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK 50
103-
#define PREFETCH_QUEUE_COUNT_STEP 4
102+
#define EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK 50
103+
#define PREFETCH_QUEUE_COUNT_STEP 4
104+
#define EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ 0x3F
104105

105106
/* TODO: This is work around and this needs to be auto generated from ODS */
106107
/** EQDMA_CPM5_IND_REG_SEL_FMAP */
@@ -2399,7 +2400,7 @@ static void eqdma_cpm5_fill_intr_ctxt(struct qdma_indirect_intr_ctxt
23992400
int eqdma_cpm5_set_default_global_csr(void *dev_hndl)
24002401
{
24012402
/* Default values */
2402-
uint32_t cfg_val = 0, reg_val = 0;
2403+
uint32_t reg_val = 0;
24032404
uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385,
24042405
513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385};
24052406
uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25,
@@ -2451,14 +2452,13 @@ int eqdma_cpm5_set_default_global_csr(void *dev_hndl)
24512452
0, QDMA_NUM_C2H_BUFFER_SIZES, buf_sz);
24522453

24532454
/* C2h Completion Coalesce Configuration */
2454-
cfg_val = qdma_reg_read(dev_hndl,
2455-
EQDMA_CPM5_C2H_WRB_COAL_BUF_DEPTH_ADDR);
24562455
reg_val =
24572456
FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK,
2458-
DEFAULT_CMPT_COAL_TIMER_CNT) |
2457+
DEFAULT_CMPT_COAL_TIMER_CNT) |
24592458
FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK,
2460-
DEFAULT_CMPT_COAL_TIMER_TICK) |
2461-
FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, cfg_val);
2459+
DEFAULT_CMPT_COAL_TIMER_TICK) |
2460+
FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK,
2461+
EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ);
24622462
qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR,
24632463
reg_val);
24642464
}

‎QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2560,7 +2560,7 @@ static int dump_eqdma_context(struct qdma_descq_context *queue_context,
25602560
int n;
25612561
int len = 0;
25622562
int rv;
2563-
char banner[DEBGFS_LINE_SZ];
2563+
char banner[DEBGFS_LINE_SZ] = "";
25642564

25652565
if (queue_context == NULL) {
25662566
qdma_log_error("%s: queue_context is NULL, err:%d\n",

‎QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737

3838
#define QDMA_VERSION_MAJOR 2023
3939
#define QDMA_VERSION_MINOR 1
40-
#define QDMA_VERSION_PATCH 1
40+
#define QDMA_VERSION_PATCH 2
4141

4242
#define QDMA_VERSION_STR \
4343
__stringify(QDMA_VERSION_MAJOR) "." \

‎QDMA/DPDK/drivers/net/qdma/qdma_devops.c‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -379,6 +379,13 @@ int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
379379
rxq->dev = dev;
380380
rxq->st_mode = qdma_dev->q_info[rx_queue_id].queue_mode;
381381

382+
/* Override rx_pkt_burst with direct call based on st or mm mode */
383+
if (rxq->st_mode) {
384+
dev->rx_pkt_burst = (qdma_dev->rx_vec_allowed) ?
385+
&qdma_recv_pkts_st_vec : &qdma_recv_pkts_st;
386+
} else
387+
dev->rx_pkt_burst = &qdma_recv_pkts_mm;
388+
382389
rxq->nb_rx_desc = (nb_rx_desc + 1);
383390
/* <= 2018.2 IP
384391
* double the cmpl ring size to avoid run out of cmpl entry while
@@ -752,6 +759,13 @@ int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
752759

753760
txq->st_mode = qdma_dev->q_info[tx_queue_id].queue_mode;
754761

762+
/* Override tx_pkt_burst with direct call based on st or mm mode */
763+
if (txq->st_mode) {
764+
dev->tx_pkt_burst = (qdma_dev->tx_vec_allowed) ?
765+
&qdma_xmit_pkts_st_vec : &qdma_xmit_pkts_st;
766+
} else
767+
dev->tx_pkt_burst = &qdma_xmit_pkts_mm;
768+
755769
txq->en_bypass = (qdma_dev->q_info[tx_queue_id].tx_bypass_mode) ? 1 : 0;
756770
txq->bypass_desc_sz = qdma_dev->q_info[tx_queue_id].tx_bypass_desc_sz;
757771

@@ -1954,10 +1968,11 @@ void qdma_dev_ops_init(struct rte_eth_dev *dev)
19541968
{
19551969
dev->dev_ops = &qdma_eth_dev_ops;
19561970
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1957-
dev->rx_pkt_burst = &qdma_recv_pkts;
1958-
dev->tx_pkt_burst = &qdma_xmit_pkts;
1971+
qdma_set_rx_function(dev);
1972+
qdma_set_tx_function(dev);
19591973
dev->rx_queue_count = &qdma_dev_rx_queue_count;
19601974
dev->rx_descriptor_status = &qdma_dev_rx_descriptor_status;
19611975
dev->tx_descriptor_status = &qdma_dev_tx_descriptor_status;
19621976
}
19631977
}
1978+

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