Merge remote-tracking branch 'origin/feature/AddCLSToken' into feature/SelectToken

Author: ollycassidy13

docs/finn/components/rtl-swg.rst

@@ -96,7 +96,7 @@ Dynamic Mode
 The "default" style also supports a dynamic mode, which provides an interface to change feature map dimensions, stride, or dilation at run-time. See `this pull request <https://github.com/Xilinx/finn/pull/688>`_ for more information.
 
 Folding
--------
+=======
 
 The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:mod:`finn.transformation.fpgadataflow.set_folding.SetFolding`). Consider the following implications:
 

docs/finn/developers.rst

@@ -99,7 +99,7 @@ computer, and you should be able to launch the various .tcl scripts or .xpr proj
 Docker container as well.
 
 Linting
--------
+=======
 
 We use a pre-commit hook to auto-format Python code and check for issues.
 See https://pre-commit.com/ for installation. Once you have pre-commit, you can install

docs/finn/source_code/finn.builder.rst

@@ -3,7 +3,7 @@ Builder
 *******
 
 Modules
-~~~~~~~
+=======
 
 finn.builder.build\_dataflow
 ----------------------------

docs/finn/source_code/finn.core.rst

@@ -3,7 +3,7 @@ Core
 ****
 
 Modules
-~~~~~~~
+=======
 
 qonnx.core.data\_layout
 -------------------------

docs/finn/source_code/finn.rst

@@ -6,7 +6,7 @@ The FINN sources are divided into different modules. They are listed below.
 .. note:: **Some of these functions and modules are located in the `qonnx` repository.**
 
 Modules
-~~~~~~~
+=======
 
 .. toctree::
    :maxdepth: 1

src/finn/custom_op/fpgadataflow/rtl/addclstoken_rtl.py

@@ -135,6 +135,10 @@ def get_rtl_file_list(self, abspath=False):
         ]
         return verilog_files
 
+    def get_rtlsim_input_indices(self):
+        """Only patch tokens are streamed; CLS token data is embedded in generated RTL."""
+        return [0]
+
     def code_generation_ipi(self):
         code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
         sourcefiles = self.get_rtl_file_list()

src/finn/custom_op/fpgadataflow/rtlbackend.py

@@ -85,17 +85,21 @@ def code_generation_ipi(self):
     def code_generation_ipgen(self, model, fpgapart, clk):
         self.generate_hdl(model, fpgapart, clk)
 
+    def get_rtlsim_input_indices(self):
+        """Return ONNX input indices that are driven as RTLSim input streams."""
+        return range(len(self.onnx_node.input))
+
     def execute_node(self, context, graph):
         mode = self.get_nodeattr("exec_mode")
         code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
 
         if mode == "rtlsim":
             node = self.onnx_node
             inputs = {}
-            for i, inp in enumerate(node.input):
+            for i in self.get_rtlsim_input_indices():
+                inp = node.input[i]
                 nbits = self.get_instream_width(i)
-                if nbits == 0:
-                    continue
+                assert nbits > 0, "RTLSim input stream %d has zero width." % i
                 exp_ishape = tuple(self.get_normal_input_shape(i))
                 folded_ishape = self.get_folded_input_shape(i)
                 inp_val = context[inp]

src/finn/transformation/fpgadataflow/specialize_layers.py

@@ -389,7 +389,6 @@ def apply(self, model):
                 node.input,
                 node.output,
                 domain="finn.custom_op.fpgadataflow." + impl_style,
-                name=node.name,
             )
             # add all attributes
             for attribute in node.attribute:

tests/fpgadataflow/test_fpgadataflow_addclstoken.py

@@ -120,13 +120,17 @@ def _prepare_addclstoken_stitched_ip_model(simd=1, pad_tokens=0):
     return model, cls_values
 
 
+def _make_input_dict(model, patches):
+    return {model.graph.input[0].name: patches}
+
+
 @pytest.mark.fpgadataflow
 def test_convert_concat_to_addclstoken():
     model, cls_values = _make_concat_model()
     patches = np.arange(12, dtype=np.float32).reshape(1, 3, 4)
     expected = np.concatenate([cls_values, patches], axis=1)
 
-    ret = execute_onnx(model, {"patches": patches})
+    ret = execute_onnx(model, _make_input_dict(model, patches))
     assert (ret["out"] == expected).all()
 
     model = model.transform(InferAddCLSTokenLayer())
@@ -139,13 +143,13 @@ def test_convert_concat_to_addclstoken():
     assert inst.get_normal_output_shape() == (1, 4, 4)
     assert inst.get_exp_cycles() == 16
 
-    ret = execute_onnx(model, {"patches": patches})
+    ret = execute_onnx(model, _make_input_dict(model, patches))
     assert (ret["out"] == expected).all()
 
     model = model.transform(SpecializeLayers(FPGA_PART))
+    model = model.transform(GiveUniqueNodeNames())
     assert model.graph.node[0].op_type == "AddCLSToken_rtl"
     assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.rtl"
-    assert model.graph.node[0].name == "AddCLSToken_concat_cls"
 
 
 @pytest.mark.fpgadataflow
@@ -157,7 +161,7 @@ def test_addclstoken_python_execution_with_padding():
         axis=1,
     )
 
-    ret = execute_onnx(model, {"patches": patches})
+    ret = execute_onnx(model, _make_input_dict(model, patches))
     assert (ret["out"] == expected).all()
 
 
@@ -178,14 +182,15 @@ def test_addclstoken_rtl_codegen(tmp_path, finn_dtype, cls_values, expected_cls_
         cls_values=cls_values,
     )
     model = model.transform(SpecializeLayers(FPGA_PART))
+    model = model.transform(GiveUniqueNodeNames())
 
     node = model.graph.node[0]
     inst = getCustomOp(node)
     inst.set_nodeattr("code_gen_dir_ipgen", str(tmp_path))
     inst.code_generation_ipgen(model, FPGA_PART, CLK_NS)
 
     topname = inst.get_nodeattr("gen_top_module")
-    assert topname == "AddCLSToken_0"
+    assert topname == node.name
     wrapper = tmp_path / (topname + ".v")
     core = tmp_path / "addclstoken.sv"
     assert wrapper.is_file()
@@ -244,7 +249,7 @@ def test_addclstoken_rtlsim(simd, pad_tokens):
     model = model.transform(SetExecMode("rtlsim"))
     model = model.transform(PrepareRTLSim())
 
-    ret = execute_onnx(model, {"patches": patches})
+    ret = execute_onnx(model, _make_input_dict(model, patches))
     assert (ret["out"] == expected).all()
 
     node = model.get_nodes_by_op_type("AddCLSToken_rtl")[0]
@@ -273,7 +278,7 @@ def test_addclstoken_stitched_ip_rtlsim(simd, pad_tokens):
 
     model.set_metadata_prop("exec_mode", "rtlsim")
 
-    ret = execute_onnx(model, {"patches": patches})
+    ret = execute_onnx(model, _make_input_dict(model, patches))
     assert (ret["out"] == expected).all()