Merge pull request #989 from LinusJungemann/feature/integrateCppDriver

Add C++ driver support

Author: auphelia

docs/finn/command_line.rst

@@ -81,7 +81,7 @@ as it goes through numerous steps:
   Running step: step_measure_rtlsim_performance [15/19]
   Running step: step_out_of_context_synthesis [16/19]
   Running step: step_synthesize_bitfile [17/19]
-  Running step: step_make_pynq_driver [18/19]
+  Running step: step_make_driver [18/19]
   Running step: step_deployment_package [19/19]
 
 

docs/finn/hw_build.rst

@@ -35,7 +35,7 @@ To rapidly test the generated design on PYNQ platforms, FINN is capable of
 generating a Python driver for the given design. This driver packs/unpacks the
 input/output tensors in the expected format, then uses PYNQ APIs to initiate
 data movement and transfer back the results to the host CPU. The generation of
-the driver is done by transformation pass :py:mod:`finn.transformation.fpgadataflow.make_pynq_driver.MakePYNQDriver`.
+the driver is done by transformation pass :py:mod:`finn.transformation.fpgadataflow.make_driver.MakePYNQDriver`.
 
 DMA and DWC Node Insertion
 ---------------------------

docs/finn/source_code/finn.transformation.fpgadataflow.rst

@@ -149,7 +149,7 @@ finn.transformation.fpgadataflow.insert\_tlastmarker
 finn.transformation.fpgadataflow.make\_pynq\_driver
 ----------------------------------------------------------
 
-.. automodule:: finn.transformation.fpgadataflow.make_pynq_driver
+.. automodule:: finn.transformation.fpgadataflow.make_driver
    :members:
    :undoc-members:
    :show-inheritance:

notebooks/advanced/4_advanced_builder_settings.ipynb

@@ -1565,7 +1565,7 @@
    "metadata": {},
    "source": [
     "You can see that after the generation of the estimate reports, the code generation and the ip generation is invoked (`step_hw_codegen` and `step_hw_ipgen`). The FIFO depths are determined and the FIFOs are inserted in the network (`step_set_fifo_depths`), we can then create an IP design of our whole network by stitching the IPs from each layer together (`step_create_stitched_ip`). At this point we have an implementation of the neural network that we can integrate within a bigger FPGA design, we can run performance measurements using simulation (`step_measure_rtlsim_performance`) and out-of-context synthesis (`step_out_of_context_synthesis`) for it.\n",
-    "The FINN builder also provides automatic system integration for Zynq and Alveo devices, this can be invoked by running `step_synthesize_bitfile`, `step_make_pynq_driver` and `step_deployment_package`."
+    "The FINN builder also provides automatic system integration for Zynq and Alveo devices, this can be invoked by running `step_synthesize_bitfile`, `step_make_driver` and `step_deployment_package`."
    ]
   },
   {
@@ -1782,7 +1782,7 @@
     "    \"step_measure_rtlsim_performance\",\n",
     "    \"step_out_of_context_synthesis\",\n",
     "    \"step_synthesize_bitfile\",\n",
-    "    \"step_make_pynq_driver\",\n",
+    "    \"step_make_driver\",\n",
     "    \"step_deployment_package\",\n",
     "]\n",
     "\n",

notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb

@@ -456,7 +456,7 @@
    "metadata": {},
    "outputs": [],
    "source": [
-    "from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver\n",
+    "from finn.transformation.fpgadataflow.make_driver import MakePYNQDriver\n",
     "model = model.transform(MakePYNQDriver(\"zynq-iodma\"))"
    ]
   },

notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb

@@ -751,7 +751,7 @@
    "metadata": {},
    "outputs": [],
    "source": [
-    "from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver\n",
+    "from finn.transformation.fpgadataflow.make_driver import MakePYNQDriver\n",
     "model = model.transform(MakePYNQDriver(\"zynq-iodma\"))"
    ]
   },

src/finn/builder/build_dataflow_config.py

@@ -62,6 +62,7 @@ class DataflowOutputType(str, Enum):
     RTLSIM_PERFORMANCE = "rtlsim_performance"
     BITFILE = "bitfile"
     PYNQ_DRIVER = "pynq_driver"
+    CPP_DRIVER = "cpp_driver"
     DEPLOYMENT_PACKAGE = "deployment_package"
 
 
@@ -123,7 +124,7 @@ class VerificationStepType(str, Enum):
     "step_measure_rtlsim_performance",
     "step_out_of_context_synthesis",
     "step_synthesize_bitfile",
-    "step_make_pynq_driver",
+    "step_make_driver",
     "step_deployment_package",
 ]
 
@@ -356,6 +357,11 @@ class DataflowBuildConfig:
     #: rtlsim, otherwise they will be replaced by RTL implementations.
     rtlsim_use_vivado_comps: Optional[bool] = True
 
+    #: Determine if the C++ driver should be generated instead of the PYNQ driver
+    #: If set to latest newest version will be used
+    #: If set to commit hash specified version will be used
+    cpp_driver_version: Optional[str] = "latest"
+
     def _resolve_hls_clk_period(self):
         if self.hls_clk_period_ns is None:
             # use same clk for synth and hls if not explicitly specified

src/finn/builder/build_dataflow_steps.py

@@ -31,6 +31,7 @@
 import numpy as np
 import os
 import shutil
+import warnings
 from copy import deepcopy
 from functools import partial
 from qonnx.core.modelwrapper import ModelWrapper
@@ -87,7 +88,7 @@
 from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
 from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
 from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
-from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.make_driver import MakeCPPDriver, MakePYNQDriver
 from finn.transformation.fpgadataflow.make_zynq_proj import ZynqBuild
 from finn.transformation.fpgadataflow.minimize_accumulator_width import (
     MinimizeAccumulatorWidth,
@@ -732,15 +733,31 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
     return model
 
 
-def step_make_pynq_driver(model: ModelWrapper, cfg: DataflowBuildConfig):
-    """Create a PYNQ Python driver that can be used to interface the generated
-    accelerator."""
+def step_make_driver(model: ModelWrapper, cfg: DataflowBuildConfig):
+    """Create a driver that can be used to interface the generated accelerator.
+    Use DataflowBuildConfig to select PYNQ Python or C++ driver."""
 
+    driver_dir = os.path.join(cfg.output_dir, "driver")
     if DataflowOutputType.PYNQ_DRIVER in cfg.generate_outputs:
-        driver_dir = cfg.output_dir + "/driver"
+        # generate PYNQ driver
         model = model.transform(MakePYNQDriver(cfg._resolve_driver_platform()))
         shutil.copytree(model.get_metadata_prop("pynq_driver_dir"), driver_dir, dirs_exist_ok=True)
         print("PYNQ Python driver written into " + driver_dir)
+    elif DataflowOutputType.CPP_DRIVER in cfg.generate_outputs:
+        # generate C++ Driver
+        model = model.transform(
+            MakeCPPDriver(
+                cfg._resolve_driver_platform(),
+                version=cfg.cpp_driver_version,
+            )
+        )
+        shutil.copytree(model.get_metadata_prop("cpp_driver_dir"), driver_dir, dirs_exist_ok=True)
+        print("C++ driver written into " + driver_dir)
+    else:
+        warnings.warn(
+            "The step step_make_driver is in the build list but will not be executed"
+            + " since no driver is selected in generate_outputs in your build.py file!"
+        )
     return model
 
 
@@ -862,7 +879,7 @@ def step_deployment_package(model: ModelWrapper, cfg: DataflowBuildConfig):
     "step_set_fifo_depths": step_set_fifo_depths,
     "step_create_stitched_ip": step_create_stitched_ip,
     "step_measure_rtlsim_performance": step_measure_rtlsim_performance,
-    "step_make_pynq_driver": step_make_pynq_driver,
+    "step_make_driver": step_make_driver,
     "step_out_of_context_synthesis": step_out_of_context_synthesis,
     "step_synthesize_bitfile": step_synthesize_bitfile,
     "step_deployment_package": step_deployment_package,