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Commit aa91e40

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Lukas Stasytis
committed
Merge remote-tracking branch 'upstream/dev' into feature/analytical-fifo-sizing
2 parents 9a388f1 + 10bf54b commit aa91e40

51 files changed

Lines changed: 1234 additions & 749 deletions

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‎docker/Dockerfile.finn‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ RUN pip install pytest-metadata==1.7.0
118118
RUN pip install pytest-html==3.0.0
119119
RUN pip install pytest-html-merger==0.0.8
120120
RUN pip install pytest-cov==4.1.0
121+
RUN pip install pyyaml==6.0.1
121122

122123
# extra dependencies from other FINN deps
123124
# installed in Docker image to make entrypoint script go faster

‎docker/jenkins/Jenkinsfile‎

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ pipeline {
9393
cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR)
9494

9595
// Pass in the marker to run with pytest and the XML test results filename
96-
runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}", "--cov --cov-report=html:coverage_fpgadataflow")
96+
runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}", "--cov --cov-report=html:coverage_fpgadataflow -n ${env.NUM_PYTEST_WORKERS} --dist worksteal")
9797

9898
// Stash the test results file(s)
9999
stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html"
@@ -324,21 +324,17 @@ void runDockerPytestWithMarker(String marker, String testResultsFilename, String
324324
sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}"""
325325
}
326326

327-
def findBoardBuildFiles(String searchDir, String dirToFind) {
328-
def result = sh(script: "find $searchDir -type d -name \"$dirToFind*\"", returnStdout: true).trim()
329-
if (result.empty) {
330-
error "Directory containing '$dirToFind' not found."
331-
}
332-
return result
333-
}
334-
335327
void findCopyZip(String board, String findDir, String copyDir) {
336-
def buildDir = findBoardBuildFiles(findDir, "hw_deployment_${board}")
337-
sh "cp -r ${buildDir}/${board} ${copyDir}/"
338-
dir(copyDir) {
339-
sh "zip -r ${board}.zip ${board}/"
340-
sh "mkdir -p ${env.ARTIFACT_DIR}/${copyDir}/"
341-
sh "cp ${board}.zip ${env.ARTIFACT_DIR}/${copyDir}/"
328+
sh "mkdir -p ${copyDir}"
329+
try {
330+
sh "cp -r ${findDir}/hw_deployment_*/${board} ${copyDir}/"
331+
dir(copyDir) {
332+
sh "zip -r ${board}.zip ${board}/"
333+
sh "mkdir -p ${env.ARTIFACT_DIR}/${copyDir}/"
334+
sh "cp ${board}.zip ${env.ARTIFACT_DIR}/${copyDir}/"
335+
}
336+
} catch (err) {
337+
error "No ${board} hw_deployment_* build artifacts found in ${findDir}"
342338
}
343339
}
344340

‎fetch-repos.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
QONNX_COMMIT="2281a777d84aa5cbd7469085c2e534fb4a03ccf9"
3131
FINN_EXP_COMMIT="0724be21111a21f0d81a072fccc1c446e053f851"
32-
BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db"
32+
BREVITAS_COMMIT="d4834bd2a0fad3c1fbc0ff7e1346d5dcb3797ea4"
3333
PYVERILATOR_COMMIT="ce0a08c20cb8c1d1e84181d6f392390f846adbd1"
3434
CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4"
3535
HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3"

‎finn-rtllib/fifo/hdl/Q_srl.v‎

Lines changed: 81 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,15 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
119119
reg i_b_reg // - true iff !full
120120
/* synthesis syn_allow_retiming=0 */ ;
121121

122+
// Parameter Checking
123+
initial begin
124+
if(depth < 2) begin
125+
$error("%m: FIFO depth must be two or higher.");
126+
$finish;
127+
end
128+
end
129+
130+
122131
assign addr_full_ = (state_==state_more) && (addr_==depth-2);
123132
// - queue full
124133
assign addr_zero_ = (addr==0); // - queue contains 2 (or 1,0)
@@ -184,58 +193,58 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
184193
end // always @ (posedge clock or negedge reset)
185194

186195
always @* begin // - combi always
187-
srlo_ <= 'bx;
188-
shift_en_o_ <= 1'bx;
189-
shift_en_ <= 1'bx;
190-
addr_ <= 'bx;
191-
state_ <= 2'bx;
196+
srlo_ = 'bx;
197+
shift_en_o_ = 1'bx;
198+
shift_en_ = 1'bx;
199+
addr_ = 'bx;
200+
state_ = 2'bx;
192201
case (state)
193202

194203
state_empty: begin // - (empty, will not produce)
195204
if (i_v) begin // - empty & i_v => consume
196-
srlo_ <= i_d;
197-
shift_en_o_ <= 1;
198-
shift_en_ <= 1'bx;
199-
addr_ <= 0;
200-
state_ <= state_one;
205+
srlo_ = i_d;
206+
shift_en_o_ = 1;
207+
shift_en_ = 1'bx;
208+
addr_ = 0;
209+
state_ = state_one;
201210
end
202211
else begin // - empty & !i_v => idle
203-
srlo_ <= 'bx;
204-
shift_en_o_ <= 0;
205-
shift_en_ <= 1'bx;
206-
addr_ <= 0;
207-
state_ <= state_empty;
212+
srlo_ = 'bx;
213+
shift_en_o_ = 0;
214+
shift_en_ = 1'bx;
215+
addr_ = 0;
216+
state_ = state_empty;
208217
end
209218
end
210219

211220
state_one: begin // - (contains one)
212221
if (i_v && o_b) begin // - one & i_v & o_b => consume
213-
srlo_ <= 'bx;
214-
shift_en_o_ <= 0;
215-
shift_en_ <= 1;
216-
addr_ <= 0;
217-
state_ <= state_more;
222+
srlo_ = 'bx;
223+
shift_en_o_ = 0;
224+
shift_en_ = 1;
225+
addr_ = 0;
226+
state_ = state_more;
218227
end
219228
else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod
220-
srlo_ <= i_d;
221-
shift_en_o_ <= 1;
222-
shift_en_ <= 1;
223-
addr_ <= 0;
224-
state_ <= state_one;
229+
srlo_ = i_d;
230+
shift_en_o_ = 1;
231+
shift_en_ = 1;
232+
addr_ = 0;
233+
state_ = state_one;
225234
end
226235
else if (!i_v && o_b) begin // - one & !i_v & o_b => idle
227-
srlo_ <= 'bx;
228-
shift_en_o_ <= 0;
229-
shift_en_ <= 1'bx;
230-
addr_ <= 0;
231-
state_ <= state_one;
236+
srlo_ = 'bx;
237+
shift_en_o_ = 0;
238+
shift_en_ = 1'bx;
239+
addr_ = 0;
240+
state_ = state_one;
232241
end
233242
else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce
234-
srlo_ <= 'bx;
235-
shift_en_o_ <= 0;
236-
shift_en_ <= 1'bx;
237-
addr_ <= 0;
238-
state_ <= state_empty;
243+
srlo_ = 'bx;
244+
shift_en_o_ = 0;
245+
shift_en_ = 1'bx;
246+
addr_ = 0;
247+
state_ = state_empty;
239248
end
240249
end // case: state_one
241250

@@ -244,60 +253,60 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
244253
// - (full, will not consume)
245254
// - (full here if depth==2)
246255
if (o_b) begin // - full & o_b => idle
247-
srlo_ <= 'bx;
248-
shift_en_o_ <= 0;
249-
shift_en_ <= 0;
250-
addr_ <= addr;
251-
state_ <= state_more;
256+
srlo_ = 'bx;
257+
shift_en_o_ = 0;
258+
shift_en_ = 0;
259+
addr_ = addr;
260+
state_ = state_more;
252261
end
253262
else begin // - full & !o_b => produce
254-
srlo_ <= srl[addr];
255-
shift_en_o_ <= 1;
256-
shift_en_ <= 0;
257-
// addr_ <= addr-1;
258-
// state_ <= state_more;
259-
addr_ <= addr_zero_ ? 0 : addr-1;
260-
state_ <= addr_zero_ ? state_one : state_more;
263+
srlo_ = srl[addr];
264+
shift_en_o_ = 1;
265+
shift_en_ = 0;
266+
// addr_ = addr-1;
267+
// state_ = state_more;
268+
addr_ = addr_zero_ ? 0 : addr-1;
269+
state_ = addr_zero_ ? state_one : state_more;
261270
end
262271
end
263272
else begin // - (mid: neither empty nor full)
264273
if (i_v && o_b) begin // - mid & i_v & o_b => consume
265-
srlo_ <= 'bx;
266-
shift_en_o_ <= 0;
267-
shift_en_ <= 1;
268-
addr_ <= addr+1;
269-
state_ <= state_more;
274+
srlo_ = 'bx;
275+
shift_en_o_ = 0;
276+
shift_en_ = 1;
277+
addr_ = addr+1;
278+
state_ = state_more;
270279
end
271280
else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod
272-
srlo_ <= srl[addr];
273-
shift_en_o_ <= 1;
274-
shift_en_ <= 1;
275-
addr_ <= addr;
276-
state_ <= state_more;
281+
srlo_ = srl[addr];
282+
shift_en_o_ = 1;
283+
shift_en_ = 1;
284+
addr_ = addr;
285+
state_ = state_more;
277286
end
278287
else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle
279-
srlo_ <= 'bx;
280-
shift_en_o_ <= 0;
281-
shift_en_ <= 0;
282-
addr_ <= addr;
283-
state_ <= state_more;
288+
srlo_ = 'bx;
289+
shift_en_o_ = 0;
290+
shift_en_ = 0;
291+
addr_ = addr;
292+
state_ = state_more;
284293
end
285294
else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce
286-
srlo_ <= srl[addr];
287-
shift_en_o_ <= 1;
288-
shift_en_ <= 0;
289-
addr_ <= addr_zero_ ? 0 : addr-1;
290-
state_ <= addr_zero_ ? state_one : state_more;
295+
srlo_ = srl[addr];
296+
shift_en_o_ = 1;
297+
shift_en_ = 0;
298+
addr_ = addr_zero_ ? 0 : addr-1;
299+
state_ = addr_zero_ ? state_one : state_more;
291300
end
292301
end // else: !if(addr_full)
293302
end // case: state_more
294303

295304
default: begin
296-
srlo_ <= 'bx;
297-
shift_en_o_ <= 1'bx;
298-
shift_en_ <= 1'bx;
299-
addr_ <= 'bx;
300-
state_ <= 2'bx;
305+
srlo_ = 'bx;
306+
shift_en_o_ = 1'bx;
307+
shift_en_ = 1'bx;
308+
addr_ = 'bx;
309+
state_ = 2'bx;
301310
end // case: default
302311

303312
endcase // case(state)

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