Merge pull request #1587 from Xilinx/deprecate/omx

Replace oh-my-xilinx with built-in OOC synthesis in CreateStitchedIP

Author: auphelia

docker/Dockerfile.finn

@@ -57,7 +57,6 @@ RUN apt-get update && \
     libzmq3-dev \
     libpixman-1-0 \
     nano \
-    zsh \
     rsync \
     git \
     openssh-client \

docker/finn_entrypoint.sh

@@ -35,7 +35,6 @@ export LC_ALL="en_US.UTF-8"
 export LANGUAGE="en_US:en"
 # colorful terminal output
 export PS1='\[\033[1;36m\]\u\[\033[1;31m\]@\[\033[1;32m\]\h:\[\033[1;35m\]\w\[\033[1;31m\]\$\[\033[0m\] '
-export PATH=$PATH:$OHMYXILINX
 
 YELLOW='\033[0;33m'
 GREEN='\033[0;32m'

fetch-repos.sh

@@ -33,7 +33,6 @@ FINN_EXP_COMMIT="0724be21111a21f0d81a072fccc1c446e053f851"
 BREVITAS_COMMIT="aad4d5a293db6f2ec622a92a5d3278e47072453e"
 CNPY_COMMIT="8c82362372ce600bbd1cf11d64661ab69d38d7de"
 HLSLIB_COMMIT="a2cd3e6ce653a03e59af6bcb9fbeaa71618d160e"
-OMX_COMMIT="a5d48f93309b235fdd21556d16e86e6ef5db6e2e"
 AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b"
 XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
 RFSOC4x2_BDF_COMMIT="13fb6f6c02c7dfd7e4b336b18b959ad5115db696"
@@ -46,7 +45,6 @@ FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git"
 BREVITAS_URL="https://github.com/Xilinx/brevitas.git"
 CNPY_URL="https://github.com/maltanar/cnpy.git"
 HLSLIB_URL="https://github.com/Xilinx/finn-hlslib.git"
-OMX_URL="https://github.com/maltanar/oh-my-xilinx.git"
 AVNET_BDF_URL="https://github.com/Avnet/bdf.git"
 XIL_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
 RFSOC4x2_BDF_URL="https://github.com/RealDigitalOrg/RFSoC4x2-BSP.git"
@@ -58,7 +56,6 @@ FINN_EXP_DIR="finn-experimental"
 BREVITAS_DIR="brevitas"
 CNPY_DIR="cnpy"
 HLSLIB_DIR="finn-hlslib"
-OMX_DIR="oh-my-xilinx"
 AVNET_BDF_DIR="avnet-bdf"
 XIL_BDF_DIR="xil-bdf"
 RFSOC4x2_BDF_DIR="rfsoc4x2-bdf"
@@ -122,7 +119,6 @@ fetch_repo $FINN_EXP_URL $FINN_EXP_COMMIT $FINN_EXP_DIR
 fetch_repo $BREVITAS_URL $BREVITAS_COMMIT $BREVITAS_DIR
 fetch_repo $CNPY_URL $CNPY_COMMIT $CNPY_DIR
 fetch_repo $HLSLIB_URL $HLSLIB_COMMIT $HLSLIB_DIR
-fetch_repo $OMX_URL $OMX_COMMIT $OMX_DIR
 fetch_repo $AVNET_BDF_URL $AVNET_BDF_COMMIT $AVNET_BDF_DIR
 fetch_repo $XIL_BDF_URL $XIL_BDF_COMMIT $XIL_BDF_DIR
 fetch_repo $RFSOC4x2_BDF_URL $RFSOC4x2_BDF_COMMIT $RFSOC4x2_BDF_DIR

run-docker.sh

@@ -93,7 +93,6 @@ SCRIPTPATH=$(dirname "$SCRIPT")
 : ${FINN_DOCKER_BUILD_EXTRA=""}
 : ${FINN_SKIP_DEP_REPOS="0"}
 : ${FINN_SKIP_BOARD_FILES="0"}
-: ${OHMYXILINX="${SCRIPTPATH}/deps/oh-my-xilinx"}
 : ${NVIDIA_VISIBLE_DEVICES=""}
 : ${DOCKER_BUILDKIT="1"}
 : ${FINN_SINGULARITY=""}
@@ -253,7 +252,6 @@ DOCKER_EXEC+="-v $FINN_HOST_BUILD_DIR:$FINN_HOST_BUILD_DIR "
 DOCKER_EXEC+="-e FINN_BUILD_DIR=$FINN_HOST_BUILD_DIR "
 DOCKER_EXEC+="-e FINN_ROOT="$SCRIPTPATH" "
 DOCKER_EXEC+="-e LOCALHOST_URL=$LOCALHOST_URL "
-DOCKER_EXEC+="-e OHMYXILINX=$OHMYXILINX "
 DOCKER_EXEC+="-e NUM_DEFAULT_WORKERS=$NUM_DEFAULT_WORKERS "
 # Workaround for FlexLM issue, see:
 # https://community.flexera.com/t5/InstallAnywhere-Forum/Issues-when-running-Xilinx-tools-or-Other-vendor-tools-in-docker/m-p/245820#M10647

scripts/finn-env.sh

@@ -55,12 +55,6 @@ export FINN_HOST_BUILD_DIR="${FINN_HOST_BUILD_DIR:-/tmp/finn_local_$(whoami)}"
 export FINN_BUILD_DIR="$FINN_HOST_BUILD_DIR"
 mkdir -p "$FINN_BUILD_DIR"
 
-# Add oh-my-xilinx to PATH
-export OHMYXILINX="$FINN_ROOT/deps/oh-my-xilinx"
-if [ -d "$OHMYXILINX" ]; then
-    export PATH="$PATH:$OHMYXILINX"
-fi
-
 # Board files path
 export FINN_BOARD_FILES_PATH="$FINN_ROOT/deps/board_files"
 

scripts/install-system-deps.sh

@@ -68,7 +68,6 @@ if command -v apt-get &> /dev/null; then
         git \
         wget \
         unzip \
-        zsh \
         python3 \
         python3-pip \
         python3-venv

src/finn/builder/build_dataflow_config.py

@@ -124,7 +124,6 @@ class VerificationStepType(str, Enum):
     "step_set_fifo_depths",
     "step_create_stitched_ip",
     "step_measure_rtlsim_performance",
-    "step_out_of_context_synthesis",
     "step_synthesize_bitfile",
     "step_make_driver",
     "step_deployment_package",

src/finn/builder/build_dataflow_steps.py

@@ -119,7 +119,6 @@
 from finn.transformation.fpgadataflow.set_folding import SetFolding
 from finn.transformation.fpgadataflow.set_loop_boundary import SetLoopBoundary
 from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers
-from finn.transformation.fpgadataflow.synth_ooc import SynthOutOfContext
 from finn.transformation.fpgadataflow.transpose_decomposition import (
     InferInnerOuterShuffles,
     ShuffleDecomposition,
@@ -141,6 +140,7 @@
 from finn.util.fpgadataflow import warn_hls_rtl_dsp_conflict
 from finn.util.mlo_sim import is_mlo, mlo_prehook_func_factory
 from finn.util.test import execute_parent
+from finn.util.vivado import parse_ooc_synth_results
 
 
 def verify_step(
@@ -272,7 +272,6 @@ def prepare_for_stitched_ip_rtlsim(verify_model, cfg):
                 CreateStitchedIP(
                     cfg._resolve_fpga_part(),
                     cfg.synth_clk_period_ns,
-                    vitis=False,
                 )
             )
     else:
@@ -332,7 +331,6 @@ def prepare_loop_ops_ipgen(node, cfg):
         CreateStitchedIP(
             cfg._resolve_fpga_part(),
             cfg.synth_clk_period_ns,
-            vitis=False,
         )
     )
     node_inst.set_nodeattr("body", loop_model.graph)
@@ -1061,14 +1059,35 @@ def step_create_stitched_ip(model: ModelWrapper, cfg: DataflowBuildConfig):
 
     if DataflowOutputType.STITCHED_IP in cfg.generate_outputs:
         stitched_ip_dir = cfg.output_dir + "/stitched_ip"
+        # If OOC_SYNTH is also requested, run P&R to extract metrics
+        run_pnr = DataflowOutputType.OOC_SYNTH in cfg.generate_outputs
         model = model.transform(
             CreateStitchedIP(
                 cfg._resolve_fpga_part(),
                 cfg.synth_clk_period_ns,
-                vitis=cfg.stitched_ip_gen_dcp,
+                run_synth=cfg.stitched_ip_gen_dcp or run_pnr,
+                run_pnr=run_pnr,
                 signature=cfg.signature,
             )
         )
+        # If P&R was run, parse the OOC results and store in model metadata + write report
+        if run_pnr:
+            vivado_stitch_proj = model.get_metadata_prop("vivado_stitch_proj")
+            ooc_res_dict = parse_ooc_synth_results(vivado_stitch_proj)
+            if ooc_res_dict is not None:
+                # Calculate estimated throughput from fmax and cycle analysis
+                estimate_network_performance = model.analysis(dataflow_performance)
+                n_clock_cycles_per_sec = float(ooc_res_dict["fmax_mhz"]) * (10**6)
+                est_fps = n_clock_cycles_per_sec / estimate_network_performance["max_cycles"]
+                ooc_res_dict["estimated_throughput_fps"] = est_fps
+
+                model.set_metadata_prop("res_total_ooc_synth", str(ooc_res_dict))
+                # Write results to report directory
+                report_dir = cfg.output_dir + "/report"
+                os.makedirs(report_dir, exist_ok=True)
+                with open(report_dir + "/ooc_synth_and_timing.json", "w") as f:
+                    json.dump(ooc_res_dict, f, indent=2)
+
         # TODO copy all ip sources into output dir? as zip?
         shutil.copytree(
             model.get_metadata_prop("vivado_stitch_proj"), stitched_ip_dir, dirs_exist_ok=True
@@ -1212,35 +1231,6 @@ def step_make_driver(model: ModelWrapper, cfg: DataflowBuildConfig):
     return model
 
 
-def step_out_of_context_synthesis(model: ModelWrapper, cfg: DataflowBuildConfig):
-    """Run out-of-context synthesis and generate reports.
-    Depends on the DataflowOutputType.STITCHED_IP output product."""
-    if DataflowOutputType.OOC_SYNTH in cfg.generate_outputs:
-        assert DataflowOutputType.STITCHED_IP in cfg.generate_outputs, "OOC needs stitched IP"
-        model = model.transform(
-            SynthOutOfContext(part=cfg._resolve_fpga_part(), clk_period_ns=cfg.synth_clk_period_ns)
-        )
-        report_dir = cfg.output_dir + "/report"
-        os.makedirs(report_dir, exist_ok=True)
-        ooc_res_dict = model.get_metadata_prop("res_total_ooc_synth")
-        ooc_res_dict = eval(ooc_res_dict)
-
-        estimate_network_performance = model.analysis(dataflow_performance)
-        # add some more metrics to estimated performance
-        n_clock_cycles_per_sec = float(ooc_res_dict["fmax_mhz"]) * (10**6)
-        est_fps = n_clock_cycles_per_sec / estimate_network_performance["max_cycles"]
-        ooc_res_dict["estimated_throughput_fps"] = est_fps
-        with open(report_dir + "/ooc_synth_and_timing.json", "w") as f:
-            json.dump(ooc_res_dict, f, indent=2)
-
-    else:
-        print(
-            """DataflowOutputType.OOC_SYNTH not in requested outputs,
-            skipping step_out_of_context_synthesis."""
-        )
-    return model
-
-
 def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
     """Synthesize a bitfile for the using the specified shell flow, using either
     Vivado or Vitis, to target the specified board."""
@@ -1399,7 +1389,6 @@ def step_loop_rolling(model, cfg):
     "step_create_stitched_ip": step_create_stitched_ip,
     "step_measure_rtlsim_performance": step_measure_rtlsim_performance,
     "step_make_driver": step_make_driver,
-    "step_out_of_context_synthesis": step_out_of_context_synthesis,
     "step_synthesize_bitfile": step_synthesize_bitfile,
     "step_deployment_package": step_deployment_package,
     "step_loop_rolling": step_loop_rolling,

src/finn/transformation/fpgadataflow/alveo_build.py

@@ -258,7 +258,9 @@ def apply(self, model):
             kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns))
             kernel_model = kernel_model.transform(HLSSynthIP())
             kernel_model = kernel_model.transform(
-                CreateStitchedIP(self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True)
+                CreateStitchedIP(
+                    self.fpga_part, self.period_ns, sdp_node.onnx_node.name, run_synth=True
+                )
             )
             if self.platform == "vitis-xrt":
                 kernel_model = kernel_model.transform(CreateVitisXO(sdp_node.onnx_node.name))

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -86,13 +86,19 @@ class CreateStitchedIP(Transformation):
     The packaged block design IP can be found under the ip subdirectory.
     """
 
-    def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[]):
+    def __init__(
+        self, fpgapart, clk_ns, ip_name="finn_design", run_synth=False, run_pnr=False, signature=[]
+    ):
         super().__init__()
         self.fpgapart = fpgapart
         self.clk_ns = clk_ns
         self.ip_name = ip_name
         self.is_mlo = False
-        self.vitis = vitis
+        self.run_synth = run_synth
+        self.run_pnr = run_pnr
+        # run_pnr requires synthesis
+        if self.run_pnr and not self.run_synth:
+            self.run_synth = True
         self.signature = signature
         self.has_aximm = False
         self.aximm_idx = 0
@@ -508,7 +514,7 @@ def apply(self, model):
         model.set_metadata_prop("wrapper_filename", wrapper_filename)
         tcl.append("set_property top %s_wrapper [current_fileset]" % block_name)
         # synthesize to DCP and export stub, DCP and constraints
-        if self.vitis:
+        if self.run_synth:
             tcl.append(
                 "set_property SYNTH_CHECKPOINT_MODE Hierarchical [ get_files %s ]" % bd_filename
             )
@@ -530,6 +536,32 @@ def apply(self, model):
                 "report_utilization -hierarchical -hierarchical_depth 5 "
                 "-file %s_partition_util.rpt" % block_name
             )
+        # optionally run place & route and extract OOC metrics
+        if self.run_pnr:
+            tcl.append("")
+            tcl.append("# --- Place and Route for OOC Metrics ---")
+            tcl.append("create_clock -period %f [get_ports ap_clk]" % self.clk_ns)
+            tcl.append("opt_design")
+            tcl.append("place_design")
+            tcl.append("route_design")
+            tcl.append("")
+            tcl.append("# Write reports to files for Python-side parsing")
+            util_rpt_file = "%s/ooc_utilization.rpt" % vivado_stitch_proj_dir
+            timing_rpt_file = "%s/ooc_timing.rpt" % vivado_stitch_proj_dir
+            power_rpt_file = "%s/ooc_power.rpt" % vivado_stitch_proj_dir
+            tcl.append('report_utilization -file "%s"' % util_rpt_file)
+            tcl.append('report_timing_summary -file "%s"' % timing_rpt_file)
+            tcl.append('report_power -file "%s"' % power_rpt_file)
+            tcl.append("")
+            tcl.append("# Write metadata (clock period, Vivado version) to a simple file")
+            meta_file = "%s/ooc_metadata.txt" % vivado_stitch_proj_dir
+            tcl.append('set fp [open "%s" w]' % meta_file)
+            tcl.append('puts $fp "clk_period_ns=%f"' % self.clk_ns)
+            tcl.append('puts $fp "vivado_version=[version -short]"')
+            tcl.append("close $fp")
+            tcl.append("")
+            tcl.append("# Save routed checkpoint")
+            tcl.append("write_checkpoint %s/%s_routed.dcp" % (vivado_stitch_proj_dir, block_name))
         # export block design itself as an IP core
         block_vendor = "xilinx_finn"
         block_library = "finn"
@@ -560,7 +592,7 @@ def apply(self, model):
             "-of [ipx::get_bus_interfaces -of [ipx::current_core ]]]"
         )
         # if targeting Vitis, add some properties to the IP
-        if self.vitis:
+        if self.run_synth:
             # replace source code with dcp
             tcl.append("set_property sdx_kernel true [ipx::find_open_core %s]" % block_vlnv)
             tcl.append("set_property sdx_kernel_type rtl [ipx::find_open_core %s]" % block_vlnv)