RESNET18_4W4A resource utilisation issue

[DaZai3219]

I am working with RESNET18 model, and trying to deploy it on PYNQ-Z2 Pre-synthesis the resource utilization is well under limit. However post synthesis, resource utilization is exceeding exuberantly.
As a result, bitstream generation is failing

What is the issue? I am not applying any floorplan config and the folding factor has been set to minimum. Max fifo depth is set to 32768

ERROR: [DRC UTLZ-1] Resource utilization: FDRE over-utilized in Top Level Design (This design requires more FDRE cells than are 
available in the target device. This design requires 286728 of such cell types but only 106775 compatible sites are available in the 
target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as 
expected. If so, please consider targeting a larger device.)

ERROR: [DRC UTLZ-1] Resource utilization: LUT as Distributed RAM over-utilized in Top Level Design (This design requires more 
LUT as Distributed RAM cells than are available in the target device. This design requires 23594 of such cell types but only 17400 
compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is 
mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter 
"drc.disableLUTOverUtilError" to 1 to change this error to warning.)

ERROR: [DRC UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic 
cells than are available in the target device. This design requires 157438 of such cell types but only 53200 compatible sites are 
available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx 
primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 
1 to change this error to warning.)

ERROR: [DRC UTLZ-1] Resource utilization: LUT as Memory over-utilized in Top Level Design (This design requires more LUT as 
Memory cells than are available in the target device. This design requires 28131 of such cell types but only 17400 compatible 
sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to 
Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter 
"drc.disableLUTOverUtilError" to 1 to change this error to warning.)

ERROR: [DRC UTLZ-1] Resource utilization: LUT6 over-utilized in Top Level Design (This design requires more LUT6 cells than are 
available in the target device. This design requires 76016 of such cell types but only 53200 compatible sites are available in the 
target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as 
expected. If so, please consider targeting a larger device.)

ERROR: [DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires 
more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 310 of such cell types but only 
280 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the 
design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

ERROR: [DRC UTLZ-1] Resource utilization: Register as Flip Flop over-utilized in Top Level Design (This design requires more 
Register as Flip Flop cells than are available in the target device. This design requires 289399 of such cell types but only 106400 
compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is 
mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

ERROR: [DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells 
than are available in the target device. This design requires 185569 of such cell types but only 53200 compatible sites are 
available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx 
primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 
1 to change this error to warning.)

ERROR: [DRC UTLZ-1] Resource utilization: Slice Registers over-utilized in Top Level Design (This design requires more Slice 
Registers cells than are available in the target device. This design requires 289399 of such cell types but only 106400 compatible 
sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to 
Xilinx primitives as expected. If so, please consider targeting a larger device.)

INFO: [Vivado_Tcl 4-198] DRC finished with 9 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
INFO: [Common 17-83] Releasing license: Implementation
208 Infos, 0 Warnings, 0 Critical Warnings and 10 Errors encountered.
place_design failed
place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 5291.055 ; gain = 0.000 ; free physical = 61253 ; free virtual = 103457
ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Mon Mar  9 08:14:25 2026...
[Mon Mar  9 08:14:25 2026] impl_1 finished
WARNING: [Vivado 12-13638] Failed runs(s) : 'impl_1'
wait_on_runs: Time (s): cpu = 00:46:43 ; elapsed = 00:54:09 . Memory (MB): peak = 3171.926 ; gain = 0.000 ; free physical = 61276 ; free virtual = 103479
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Mar  9 08:14:25 2026...