Discussed in #1405
Originally posted by CarloSchafflik12 August 2, 2025
My model requires a few AXI-Lite interfaces because runtime weights are enabled. However, an error was asserted by a .tcl file while generating the bitfile:
"Maximum 10 AXI-Lite interfaces supported"
This limit is hardcoded in this file: "finn/src/transformation/fpgaflow/templates.py", which creates the .tcl file:
if {$NUM_AXILITE > 9} {
error "Maximum 10 AXI-Lite interfaces supported"
}
However, when I increase the limit to 15, for example, the bit file is generated and everything works as expected. So, my question is, why is this limit there?
Discussed in #1405
Originally posted by CarloSchafflik12 August 2, 2025
My model requires a few AXI-Lite interfaces because runtime weights are enabled. However, an error was asserted by a .tcl file while generating the bitfile:
"Maximum 10 AXI-Lite interfaces supported"
This limit is hardcoded in this file: "finn/src/transformation/fpgaflow/templates.py", which creates the .tcl file:
if {$NUM_AXILITE > 9} {
error "Maximum 10 AXI-Lite interfaces supported"
}
However, when I increase the limit to 15, for example, the bit file is generated and everything works as expected. So, my question is, why is this limit there?