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Make timeout limit for fifo sim configurable #1435

Description

@LeahLS

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Details

New behavior

It might be useful to make the timeout limit for the set-fifo-depth simulation configurable, for example using an env var like for the rtlsim liveness_treshold.

Motivation

While building the finn-examples for the AUP-ZU3 board, the issue of an fifo sim timeout occurred. Currently, this issue can only be resolved by manually modifying the code.

Parts of FINN affected

Transformation, FPGA Dataflow, Set FIFO depths

Activity

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