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Normalize source file format and unify the SIMD kernel headers
Phase A - format: 74 files converted to CRLF (10 x86_64 kernel includes, 29 library units, one test unit, the scripts tree). The repo encoding rule is valid UTF-8 without BOM; a new scripts/maintenance/check-file-format.ps1 enforces CRLF + strict UTF-8 + no BOM and the pre-commit hook chains it after the duplicate-GUID check. Phase B - headers: all 107 kernel .inc headers now follow one canonical shape: title, strategy notes, "ABI (after HlpSimdProcNBegin_<arch>.inc): ..." with layout sub-lines, register map, frame/saves, the encoding one-liner, and "Reference:" always last. Typographic punctuation in the Simd tree normalized to ASCII (BOM-less sources render non-ASCII as mojibake in the IDEs). The Common/CpuFeatures prologue includes keep their structure - per- compiler adaptation is their purpose - with punctuation normalized. Every aarch64 header was changed through its generator constant, so regeneration stays byte-idempotent (asm-check passes for all 15 generated kernels). Two stale headers were corrected: Blake2B NEON now documents its d8-d15 save/restore via the shared include, and Blake3 hash4 NEON's duplicated G-temps map lines are merged.
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110 files changed

Lines changed: 1325 additions & 1317 deletions

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‎HashLib/src/Include/Simd/Adler32/Adler32BlocksAvx2_i386.inc‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
1-
// AVX2 implementation of Adler-32 block processing (IA-32; 256-bit ymm
2-
// integer ops work in 32-bit mode - only ymm0-7 exist, which this kernel
3-
// fits). Same structure as Adler32BlocksAvx2_x86_64.inc.
4-
// IA-32: after HlpSimdProc4Begin_i386 - ebx = data ptr, esi = num_blocks,
1+
// AVX2 implementation of Adler-32 block processing (num_blocks x 32-byte blocks;
2+
// IA-32: 256-bit ymm integer ops work in 32-bit mode and only ymm0-ymm7 exist,
3+
// which this kernel fits). Same structure as Adler32BlocksAvx2_x86_64.inc.
4+
// Does NOT apply mod 65521 (the caller does).
5+
// ABI (after HlpSimdProc4Begin_i386.inc): ebx = data ptr, esi = num_blocks,
56
// edi = sums ptr, eax = constants ptr (moved to ecx at entry; eax then
67
// accumulates SumA). SumB rides xmm1 end-to-end via vmovd memory forms.
7-
// ASums layout: [SumA: UInt32, SumB: UInt32].
8-
// Constants layout: [weights: 32B, ones_16: 32B] at offsets 0 and 32.
9-
// Processes num_blocks x 32-byte blocks. Does NOT apply mod 65521 (caller does it).
10-
// Uses ymm0-ymm5 only (all volatile on IA-32; no saves needed).
8+
// Sums layout: [SumA: UInt32, SumB: UInt32].
9+
// Constants layout: [weights: 32B, ones_16: 32B] at offsets 0 and 32.
10+
// Saves: none (uses ymm0-ymm5 only; all volatile on IA-32).
1111
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
1212
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksAvx2_x86_64.inc.
1313

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksAvx2_x86_64.inc‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
1-
// AVX2 implementation of Adler-32 block processing.
2-
// Expects MS x64 ABI: rcx = data ptr, edx = num_blocks, r8 = sums ptr, r9 = constants ptr.
3-
// ASums layout: [SumA: UInt32, SumB: UInt32].
4-
// Constants layout: [weights: 32B, ones_16: 32B] at offsets 0 and 32.
5-
// Processes num_blocks x 32-byte blocks. Does NOT apply mod 65521 (caller does it).
6-
// Uses ymm0-ymm5 only (volatile under both ABIs; no saves needed).
7-
// Weights and ones are reloaded from memory each iteration to avoid
8-
// using non-volatile ymm registers.
1+
// AVX2 implementation of Adler-32 block processing (num_blocks x 32-byte blocks).
2+
// Does NOT apply mod 65521 (the caller does). Weights and ones are reloaded
3+
// from memory each iteration so no non-volatile ymm register is needed.
4+
// ABI (after HlpSimdProc4Begin_x86_64.inc): rcx = data ptr, edx = num_blocks,
5+
// r8 = sums ptr, r9 = constants ptr.
6+
// Sums layout: [SumA: UInt32, SumB: UInt32].
7+
// Constants layout: [weights: 32B, ones_16: 32B] at offsets 0 and 32.
8+
// Saves: none (uses ymm0-ymm5 only; volatile under both ABIs).
99
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
10+
// Reference: Chromium zlib adler32_simd.c.
1011

1112
// Zero register
1213
db $C5, $E5, $EF, $DB // vpxor ymm3, ymm3, ymm3

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksNeon_aarch64.inc‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
1-
// Adler-32 ProcessBlocks AArch64 NEON implementation (32-byte blocks).
2-
// Expects AAPCS64: x0 = AData, w1 = ANumBlocks, x2 = ASums, x3 = AConstants.
3-
// ASums layout: [SumA: UInt32, SumB: UInt32]. Does NOT apply mod 65521.
4-
// Constants layout matches Adler32Constants: bytes [32..1] at offset 0..31.
5-
// Leaf nostackframe; caller-saved GPR/vector only.
6-
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksSsse3_x86_64.inc.
7-
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
1+
// NEON implementation of Adler-32 block processing (num_blocks x 32-byte blocks).
2+
// Does NOT apply mod 65521 (the caller does).
3+
// ABI (after HlpSimdProc4Begin_aarch64.inc): x0 = data ptr, w1 = num_blocks,
4+
// x2 = sums ptr, x3 = constants ptr.
5+
// Sums layout: [SumA: UInt32, SumB: UInt32].
6+
// Constants layout matches Adler32Constants: bytes [32..1] at offsets 0..31.
87
// Register map:
98
// w9 = block counter (from w1)
109
// w10 = SumA in / SumA out
@@ -20,6 +19,10 @@
2019
// v24-v27 = widened weight vectors for vmlal
2120
// v28-v29 = weight byte loads from AConstants
2221
// v30 = ext scratch for weight / reduce halves
22+
// Saves: none (leaf nostackframe; caller-saved GPR/vector only).
23+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
24+
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksSsse3_x86_64.inc.
25+
2326
.long 0xb940004a // ldr w10, [x2]
2427
.long 0xb940044b // ldr w11, [x2, #4]
2528
.long 0x1b017d4c // mul w12, w10, w1

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_i386.inc‎

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,18 @@
1-
// SSE2 implementation of Adler-32 block processing (IA-32).
2-
// After HlpSimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants.
3-
// ASums: [SumA: UInt32, SumB: UInt32]. Constants: [weights_hi: 16B, weights_lo: 16B] (32 bytes).
4-
// Processes num_blocks x 32-byte blocks; caller applies mod 65521.
5-
//
6-
// x64 uses xmm6-xmm9 for widened weights; IA-32 only has xmm0-xmm7, so widened weights
7-
// live on stack (4 x 16 bytes). xmm6–xmm7 saved/restored defensively (volatile on i386).
8-
//
9-
// Same SSE2 emulation as Adler32BlocksSse2_x86_64.inc (punpcklbw/hbw + pmaddwd).
10-
//
11-
// Stack layout (sub esp, 96):
12-
// [esp + 0..15]: xmm6 save
13-
// [esp + 16..31]: xmm7 save
14-
// [esp + 32..47]: w0 (weights_hi low)
15-
// [esp + 48..63]: w1 (weights_hi high)
16-
// [esp + 64..79]: w2 (weights_lo low)
17-
// [esp + 80..95]: w3 (weights_lo high)
1+
// SSE2 implementation of Adler-32 block processing (num_blocks x 32-byte blocks;
2+
// IA-32). Does NOT apply mod 65521 (the caller does). Same SSE2 pmaddubsw
3+
// emulation as Adler32BlocksSse2_x86_64.inc (punpcklbw/hbw + pmaddwd); x64
4+
// keeps the widened weights in xmm6-xmm9, IA-32 only has xmm0-xmm7 so they
5+
// live on the stack (4 x 16 bytes).
6+
// ABI (after HlpSimdProc4Begin_i386.inc): ebx = data ptr, esi = num_blocks,
7+
// edi = sums ptr, eax = constants ptr.
8+
// Sums layout: [SumA: UInt32, SumB: UInt32].
9+
// Constants layout: [weights_hi: 16B, weights_lo: 16B] (32 bytes).
10+
// Frame (sub esp, 96):
11+
// [esp + 0..15] = xmm6 save [esp + 48..63] = w1 (weights_hi high)
12+
// [esp + 16..31] = xmm7 save [esp + 64..79] = w2 (weights_lo low)
13+
// [esp + 32..47] = w0 (weights_hi low) [esp + 80..95] = w3 (weights_lo high)
14+
// Saves: xmm6-xmm7 saved/restored defensively (volatile on IA-32).
15+
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksSse2_x86_64.inc.
1816

1917
// Preserve constants pointer (eax) before GPR reloads from ASums
2018
push eax

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_x86_64.inc‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
1-
// SSE2 implementation of Adler-32 block processing.
2-
// Expects MS x64 ABI: rcx = data ptr, edx = num_blocks, r8 = sums ptr, r9 = constants ptr.
3-
// ASums layout: [SumA: UInt32, SumB: UInt32].
4-
// Constants layout: [weights_hi: 16B, weights_lo: 16B] (only first 32 bytes used).
5-
// Processes num_blocks x 32-byte blocks. Does NOT apply mod 65521 (caller does it).
6-
// Uses xmm0-xmm9; xmm6-xmm9 are MS x64 non-volatile (saved/restored).
7-
//
8-
// Emulates SSSE3 pmaddubsw via punpcklbw/punpckhbw + pmaddwd:
9-
// data bytes are zero-extended to i16, then multiplied with pre-widened
10-
// weight bytes via pmaddwd (SSE2), producing the same 4 x i32 weighted
11-
// sums per 16-byte half that pmaddubsw + pmaddwd would yield.
1+
// SSE2 implementation of Adler-32 block processing (num_blocks x 32-byte blocks).
2+
// Does NOT apply mod 65521 (the caller does). Emulates SSSE3 pmaddubsw via
3+
// punpcklbw/punpckhbw + pmaddwd: data bytes are zero-extended to i16, then
4+
// multiplied with pre-widened weight bytes via pmaddwd (SSE2), producing the
5+
// same 4 x i32 weighted sums per 16-byte half that pmaddubsw + pmaddwd yield.
6+
// ABI (after HlpSimdProc4Begin_x86_64.inc): rcx = data ptr, edx = num_blocks,
7+
// r8 = sums ptr, r9 = constants ptr.
8+
// Sums layout: [SumA: UInt32, SumB: UInt32].
9+
// Constants layout: [weights_hi: 16B, weights_lo: 16B] (first 32 bytes used).
10+
// Saves: xmm6-xmm9 (MS x64 non-volatile) in the local frame; uses xmm0-xmm9.
11+
// Reference: Chromium zlib adler32_simd.c.
1212

1313
{$I ..\..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc}
1414

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_i386.inc‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
1-
// SSSE3 Adler-32 block processing (IA-32).
2-
// After HlpSimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants.
3-
// Constants: [weights_hi: 16B, weights_lo: 16B, ones_16: 16B] (48 bytes; same as x64 SSSE3).
4-
// No xmm8 on IA-32: psadbw uses a copy in xmm5 (first half) or xmm4 (second half), then reload weights.
5-
// Caller applies mod 65521.
6-
//
7-
// xmm6–xmm7 saved/restored defensively (volatile on i386).
1+
// SSSE3 implementation of Adler-32 block processing (num_blocks x 32-byte blocks;
2+
// IA-32). Does NOT apply mod 65521 (the caller does). No xmm8 on IA-32:
3+
// psadbw uses a copy in xmm5 (first half) or xmm4 (second half), then the
4+
// weights are reloaded.
5+
// ABI (after HlpSimdProc4Begin_i386.inc): ebx = data ptr, esi = num_blocks,
6+
// edi = sums ptr, eax = constants ptr.
7+
// Constants layout: [weights_hi: 16B, weights_lo: 16B, ones_16: 16B]
8+
// (48 bytes; same as the x64 SSSE3 kernel).
9+
// Saves: xmm6-xmm7 saved/restored defensively (volatile on IA-32).
10+
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksSsse3_x86_64.inc.
811

912
push eax
1013

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_x86_64.inc‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
1-
// SSSE3 implementation of Adler-32 block processing.
2-
// Expects MS x64 ABI: rcx = data ptr, edx = num_blocks, r8 = sums ptr, r9 = constants ptr.
3-
// ASums layout: [SumA: UInt32, SumB: UInt32].
4-
// Constants layout: [weights_hi: 16B, weights_lo: 16B, ones_16: 16B].
5-
// Processes num_blocks x 32-byte blocks. Does NOT apply mod 65521 (caller does it).
6-
// Uses xmm0-xmm8; xmm6-xmm8 are MS x64 non-volatile (saved/restored).
1+
// SSSE3 implementation of Adler-32 block processing (num_blocks x 32-byte blocks).
2+
// Does NOT apply mod 65521 (the caller does).
3+
// ABI (after HlpSimdProc4Begin_x86_64.inc): rcx = data ptr, edx = num_blocks,
4+
// r8 = sums ptr, r9 = constants ptr.
5+
// Sums layout: [SumA: UInt32, SumB: UInt32].
6+
// Constants layout: [weights_hi: 16B, weights_lo: 16B, ones_16: 16B].
7+
// Saves: xmm6-xmm8 (MS x64 non-volatile) in the local frame; uses xmm0-xmm8.
8+
// Reference: Chromium zlib adler32_simd.c.
79

810
{$I ..\..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc}
911

‎HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_i386.inc‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,22 @@
1-
// AVX2 implementation of Argon2 FillBlock (IA-32). 256-bit ymm integer ops
2-
// work in 32-bit mode; same algorithm and buffer layout as
3-
// Argon2FillBlockAvx2_x86_64.inc, redesigned for the IA-32 register budget:
1+
// AVX2 implementation of Argon2 FillBlock (BlaMka round function; IA-32).
2+
// 256-bit ymm integer ops work in 32-bit mode; same algorithm and buffer
3+
// layout as Argon2FillBlockAvx2_x86_64.inc, redesigned for the IA-32
4+
// register budget:
45
// - the byte-rotation masks are VEX memory operands (rot24 at [masks],
56
// rot16 at [masks+$20]; read unaligned, so the Pascal const needs no
6-
// special alignment) - the kernel touches only ymm0-ymm4, all volatile,
7-
// so nothing is saved;
7+
// special alignment) - the kernel touches only ymm0-ymm4;
88
// - R_buf/Z_buf sit at [esp]/[esp+1024] and are addressed [esp+edx+disp]
99
// (edx = loop offset) - no buffer pointer registers are needed;
1010
// - Left/Right are dead after step 1's XOR.
11-
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
12-
// IA-32: after HlpSimdProc5Begin_i386 - ebx = Left ptr, esi = Right ptr,
11+
// Diagonalize/Undiagonalize via vpermq. vzeroupper required before return.
12+
// ABI (after HlpSimdProc5Begin_i386.inc): ebx = Left ptr, esi = Right ptr,
1313
// edi = Current ptr, eax = WithXor (0 or 1; live until the final step),
1414
// ecx = byte-rotation masks ptr (ARGON2_ROT_MASKS; live throughout).
15-
// Each pointer addresses 128 QWords (1024 bytes).
16-
// Stack layout (sub esp, 2048): [esp+0..1023] R_buf, [esp+1024..2047] Z_buf.
17-
// ARight and ACurrent may alias; R_buf buffering handles this.
18-
// Diagonalize/Undiagonalize via vpermq (cross-lane 64-bit permute).
19-
// vzeroupper required before return.
15+
// Each pointer addresses 128 QWords (1024 bytes). ARight and ACurrent may
16+
// alias; R_buf buffering handles this.
17+
// Frame (sub esp, 2048): [esp+0..1023] R_buf, [esp+1024..2047] Z_buf.
18+
// Saves: none (uses ymm0-ymm4 only; all volatile on IA-32).
19+
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
2020
// Reference: official Argon2 AVX2 (blamka-round-opt.h), HashLib
2121
// Argon2FillBlockAvx2_x86_64.inc.
2222

‎HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_x86_64.inc‎

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,25 @@
1-
// AVX2 implementation of Argon2 FillBlock.
2-
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
3-
// Expects MS x64 ABI (after HlpSimdProc5Begin): rcx = Left ptr, rdx = Right ptr,
1+
// AVX2 implementation of Argon2 FillBlock (BlaMka round function).
2+
// Rotations: rot32 via vpshufd, rot24/16 via vpshufb against the resident
3+
// masks, rot63 via shift+or (not byte-aligned). Diagonalize/Undiagonalize
4+
// via vpermq (cross-lane 64-bit permute). vzeroupper required before return.
5+
// ABI (after HlpSimdProc5Begin_x86_64.inc): rcx = Left ptr, rdx = Right ptr,
46
// r8 = Current ptr, r9 = WithXor (0 or 1), r10 = byte-rotation masks ptr
5-
// (see ARGON2_ROT_MASKS: rot24 at +0, rot16 at +32; read unaligned, so the
6-
// Pascal const needs no special alignment; consumed by the entry mask loads,
7-
// r10 is scratch afterwards).
8-
// Each pointer addresses 128 QWords (1024 bytes).
9-
// Uses ymm0-ymm11; ymm6-ymm11 are MS x64 non-volatile (saved/restored).
10-
// Register map during G rounds: ymm0 = A(v0..v3), ymm1 = B(v4..v7),
7+
// (ARGON2_ROT_MASKS: rot24 at +0, rot16 at +32; read unaligned, so the
8+
// Pascal const needs no special alignment; consumed by the entry mask
9+
// loads, r10 is scratch afterwards).
10+
// Each pointer addresses 128 QWords (1024 bytes). ARight and ACurrent may
11+
// alias; R_buf buffering handles this. r8/r9 survive all loops.
12+
// Register map (G rounds): ymm0 = A(v0..v3), ymm1 = B(v4..v7),
1113
// ymm2 = C(v8..v11), ymm3 = D(v12..v15), ymm4-ymm5 = temps,
1214
// ymm10 = rot24 mask, ymm11 = rot16 mask.
13-
// Rotations: rot32 via vpshufd, rot24/16 via vpshufb against the resident
14-
// masks, rot63 via shift+or (not byte-aligned).
15-
// Stack layout (sub rsp, 2184):
16-
// [rsp+0..127] ymm6-9 save area (4 * 32 = 128 bytes)
17-
// [rsp+128..1151] R_buf (1024 bytes)
18-
// [rsp+1152..2175] Z_buf (1024 bytes)
19-
// [rsp+2176..2183] alignment padding
20-
// r8 (Current) and r9 (WithXor) survive all loops (not clobbered).
21-
// ARight and ACurrent may alias; R_buf buffering handles this.
22-
// Diagonalize/Undiagonalize via vpermq (cross-lane 64-bit permute).
23-
// vzeroupper required before return.
15+
// Frame (sub rsp, 2184):
16+
// [rsp+0..127] = ymm6-ymm9 save area (4 x 32 bytes)
17+
// [rsp+128..1151] = R_buf (1024 bytes)
18+
// [rsp+1152..2175] = Z_buf (1024 bytes)
19+
// [rsp+2176..2183] = alignment padding
20+
// Saves: ymm6-ymm11 (MS x64 non-volatile); uses ymm0-ymm11.
21+
// AVX/AVX2 instructions are db-encoded for broad assembler compatibility.
22+
// Reference: official Argon2 AVX2 (blamka-round-opt.h).
2423

2524
{$I ..\..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc}
2625

‎HashLib/src/Include/Simd/Argon2/Argon2FillBlockNeon_aarch64.inc‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,9 @@
1-
// Argon2 FillBlock AArch64 NEON implementation (BlaMka round function).
2-
// Expects AAPCS64: x0 = Left ptr, x1 = Right ptr, x2 = Current ptr, w3 = WithXor.
3-
// Each pointer addresses 128 UInt64 (1024 bytes).
4-
// Stack frame 2128 bytes; see register map.
5-
// Steps: R=Left XOR Right; Z=copy(R); 8 column + 8 row BlaMka rounds on Z;
6-
// Current = R XOR Z [XOR Current if WithXor]. Diagonalize via vext #8.
7-
// Reference: jedisct1/libsodium argon2-fill-block-neon.c, HashLib Argon2FillBlockSse2_x86_64.inc.
8-
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
1+
// NEON implementation of Argon2 FillBlock (BlaMka round function).
2+
// Steps: R = Left XOR Right; Z = copy(R); 8 column + 8 row BlaMka rounds on
3+
// Z; Current = R XOR Z [XOR Current if WithXor]. Diagonalize via vext #8.
4+
// ABI (after HlpSimdProc4Begin_aarch64.inc): x0 = Left ptr, x1 = Right ptr,
5+
// x2 = Current ptr, w3 = WithXor (0 or 1).
6+
// Each pointer addresses 128 QWords (1024 bytes).
97
// Register map:
108
// v0-v1 = A0, A1
119
// v2-v3 = B0, B1
@@ -18,6 +16,11 @@
1816
// x11 = Z_buf base ([sp+1088])
1917
// x12 = Z slice pointer (column/row load/store)
2018
// w3 = WithXor (0 or 1)
19+
// Frame: 2128 bytes (R_buf at [sp+64], Z_buf at [sp+1088], 16-byte SP pad).
20+
// Saves: none (caller-saved GPR/vector only).
21+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
22+
// Reference: jedisct1/libsodium argon2-fill-block-neon.c, HashLib
23+
// Argon2FillBlockSse2_x86_64.inc.
2124

2225
sub sp, sp, #2128
2326
add x9, sp, #64

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