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Xor-elXor-el
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Add AArch64 NEON implementation for Adler32 (#83)
1 parent c698884 commit 910d7df

2 files changed

Lines changed: 117 additions & 4 deletions

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‎HashLib/src/Checksum/HlpAdler32Dispatch.pas‎

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ procedure Adler32_Update_Scalar(AData: PByte; ALength: UInt32; ASums: Pointer);
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// SIMD implementations: SSE2 / SSSE3 (IA-32); SSE2 / SSSE3 / AVX2 (x86-64)
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// =============================================================================
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71-
{$IFDEF HASHLIB_X86_SIMD}
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{$IF DEFINED(HASHLIB_X86_SIMD) OR DEFINED(HASHLIB_ARM_SIMD)}
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type
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TProcessBlocksProc = procedure(AData: PByte; ANumBlocks: UInt32;
@@ -113,7 +113,9 @@ procedure Adler32_Update_Simd(AData: PByte; ALength: UInt32; ASums: Pointer;
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end;
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end;
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116-
{$ENDIF HASHLIB_X86_SIMD}
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{$ENDIF}
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{$IFDEF HASHLIB_X86_SIMD}
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{$IFDEF HASHLIB_I386_ASM}
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@@ -163,8 +165,6 @@ procedure Adler32_Update_Avx2(AData: PByte; ALength: UInt32; ASums: Pointer);
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{$ENDIF HASHLIB_X86_64_ASM}
165167

166-
{$IFDEF HASHLIB_X86_SIMD}
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procedure Adler32_Update_Sse2(AData: PByte; ALength: UInt32; ASums: Pointer);
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begin
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Adler32_Update_Simd(AData, ALength, ASums, @Adler32_ProcessBlocks_Sse2);
@@ -181,6 +181,25 @@ procedure Adler32_Update_Ssse3(AData: PByte; ALength: UInt32; ASums: Pointer);
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{$ENDIF HASHLIB_X86_SIMD}
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184+
{$IFDEF HASHLIB_AARCH64_ASM}
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procedure Adler32_ProcessBlocks_Neon(AData: PByte; ANumBlocks: UInt32;
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ASums, AConstants: Pointer);
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{$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc}
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{$I ..\Include\Simd\Adler32\Adler32BlocksNeon_aarch64.inc}
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end;
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{$IFDEF HASHLIB_ARM_SIMD}
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procedure Adler32_Update_Neon(AData: PByte; ALength: UInt32; ASums: Pointer);
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begin
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Adler32_Update_Simd(AData, ALength, ASums, @Adler32_ProcessBlocks_Neon);
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end;
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{$ENDIF HASHLIB_ARM_SIMD}
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{$ENDIF HASHLIB_AARCH64_ASM}
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// =============================================================================
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// Dispatch initialization
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// =============================================================================
@@ -216,6 +235,14 @@ procedure InitDispatch();
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end;
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end;
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{$ENDIF}
238+
{$IFDEF HASHLIB_AARCH64_ASM}
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case TCpuFeatures.Arm.SelectSlot([TArmSimdLevel.NEON]) of
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TArmSimdLevel.NEON:
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begin
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Adler32_Update := @Adler32_Update_Neon;
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end;
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end;
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{$ENDIF}
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end;
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initialization

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksNeon_aarch64.inc‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
// Adler-32 ProcessBlocks AArch64 NEON implementation (32-byte blocks).
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// Expects AAPCS64: x0 = AData, w1 = ANumBlocks, x2 = ASums, x3 = AConstants.
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// ASums layout: [SumA: UInt32, SumB: UInt32]. Does NOT apply mod 65521.
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// Constants layout matches Adler32Constants: bytes [32..1] at offset 0..31
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// (two 16-byte halves; only the weight bytes are read here).
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// Reference (golden): HashLib Adler32BlocksSsse3_x86_64.inc;
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// Chromium zlib adler32_simd.c ADLER32_SIMD_NEON column-sum + vmlal path.
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//
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// Instruction encodings (for assembler compatibility):
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// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
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// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
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// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
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// '.long' opcode, with the equivalent mnemonic in the trailing comment; only
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// neg/ret stay as text.
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//
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// Register map:
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// w9 = block counter (from w1)
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// w10 = SumA in / SumA out
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// w11 = SumB in / SumB out
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// w12 = SumA * num_blocks (v_ps lane 0 seed)
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// w13 = horizontal-reduce scratch
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// v0 = v_s1 (uint32x4 byte-sum accumulators)
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// v1 = v_s2 (uint32x4 s2 partial, SumB seeded in lane 0)
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// v4-v5 = 32 input bytes per block
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// v6-v8 = uaddlp / horizontal-reduce temps
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// v16-v19 = column sums (uint16x8)
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// v20 = v_ps (SumA*blocks + per-block v_s1), lane 0 used before <<5 add
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// v24-v27 = widened weight vectors for vmlal
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// v28-v29 = weight byte loads from AConstants
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// v30 = ext scratch for weight / reduce halves
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.long 0xb940004a // ldr w10, [x2]
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.long 0xb940044b // ldr w11, [x2, #4]
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.long 0x1b017d4c // mul w12, w10, w1
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.long 0x2a0103e9 // mov w9, w1
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.long 0x6e341e94 // eor v20.16b, v20.16b, v20.16b
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.long 0x4e041d94 // ins v20.s[0], w12
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.long 0x6e211c21 // eor v1.16b, v1.16b, v1.16b
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.long 0x4e041d61 // ins v1.s[0], w11
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.long 0x6e201c00 // eor v0.16b, v0.16b, v0.16b
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.long 0x6e301e10 // eor v16.16b, v16.16b, v16.16b
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.long 0x6e311e31 // eor v17.16b, v17.16b, v17.16b
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.long 0x6e321e52 // eor v18.16b, v18.16b, v18.16b
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.long 0x6e331e73 // eor v19.16b, v19.16b, v19.16b
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.long 0x3dc0007c // ldr q28, [x3, #0x0]
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.long 0x3dc0047d // ldr q29, [x3, #0x10]
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.Ladler_blocks_loop:
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.long 0x4ea08694 // add v20.4s, v20.4s, v0.4s
48+
.long 0x3dc00004 // ldr q4, [x0, #0x0]
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.long 0x3dc00405 // ldr q5, [x0, #0x10]
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.long 0x6e202886 // uaddlp v6.8h, v4.16b
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.long 0x6e6068c0 // uadalp v0.4s, v6.8h
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.long 0x6e2028a7 // uaddlp v7.8h, v5.16b
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.long 0x6e6068e0 // uadalp v0.4s, v7.8h
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.long 0x2e241210 // uaddw v16.8h, v16.8h, v4.8b
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.long 0x6e241231 // uaddw2 v17.8h, v17.8h, v4.16b
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.long 0x2e251252 // uaddw v18.8h, v18.8h, v5.8b
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.long 0x6e251273 // uaddw2 v19.8h, v19.8h, v5.16b
58+
.long 0x91008000 // add x0, x0, #32
59+
.long 0x71000529 // subs w9, w9, #1
60+
b.ne .Ladler_blocks_loop
61+
.long 0x4f255694 // shl v20.4s, v20.4s, #5
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.long 0x4eb48421 // add v1.4s, v1.4s, v20.4s
63+
.long 0x2f08a798 // ushll v24.8h, v28.8b, #0
64+
.long 0x6e1c439e // ext v30.16b, v28.16b, v28.16b, #8
65+
.long 0x2f08a7d9 // ushll v25.8h, v30.8b, #0
66+
.long 0x2f08a7ba // ushll v26.8h, v29.8b, #0
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.long 0x6e1d43be // ext v30.16b, v29.16b, v29.16b, #8
68+
.long 0x2f08a7db // ushll v27.8h, v30.8b, #0
69+
.long 0x2e788201 // umlal v1.4s, v16.4h, v24.4h
70+
.long 0x6e788201 // umlal2 v1.4s, v16.8h, v24.8h
71+
.long 0x2e798221 // umlal v1.4s, v17.4h, v25.4h
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.long 0x6e798221 // umlal2 v1.4s, v17.8h, v25.8h
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.long 0x2e7a8241 // umlal v1.4s, v18.4h, v26.4h
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.long 0x6e7a8241 // umlal2 v1.4s, v18.8h, v26.8h
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.long 0x2e7b8261 // umlal v1.4s, v19.4h, v27.4h
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.long 0x6e7b8261 // umlal2 v1.4s, v19.8h, v27.8h
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.long 0x4ea0bc06 // addp v6.4s, v0.4s, v0.4s
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.long 0x0ea6bcc6 // addp v6.2s, v6.2s, v6.2s
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.long 0x0e043ccd // umov w13, v6.s[0]
80+
.long 0x0b0d014a // add w10, w10, w13
81+
.long 0x4ea1bc26 // addp v6.4s, v1.4s, v1.4s
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.long 0x0ea6bcc6 // addp v6.2s, v6.2s, v6.2s
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.long 0x0e043ccb // umov w11, v6.s[0]
84+
.long 0xb900004a // str w10, [x2]
85+
.long 0xb900044b // str w11, [x2, #4]
86+
ret

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