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unify aarch64 inc files headers
1 parent 0b63d58 commit bcab5df

15 files changed

Lines changed: 71 additions & 239 deletions

‎HashLib/src/Include/Simd/Adler32/Adler32BlocksNeon_aarch64.inc‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,10 @@
11
// Adler-32 ProcessBlocks AArch64 NEON implementation (32-byte blocks).
22
// Expects AAPCS64: x0 = AData, w1 = ANumBlocks, x2 = ASums, x3 = AConstants.
33
// ASums layout: [SumA: UInt32, SumB: UInt32]. Does NOT apply mod 65521.
4-
// Constants layout matches Adler32Constants: bytes [32..1] at offset 0..31
5-
// (two 16-byte halves; only the weight bytes are read here).
6-
// Reference (golden): HashLib Adler32BlocksSsse3_x86_64.inc;
7-
// Chromium zlib adler32_simd.c ADLER32_SIMD_NEON column-sum + vmlal path.
8-
//
9-
// Instruction encodings (for assembler compatibility):
10-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
11-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
12-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
13-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only
14-
// neg/ret stay as text.
15-
//
4+
// Constants layout matches Adler32Constants: bytes [32..1] at offset 0..31.
5+
// Leaf nostackframe; caller-saved GPR/vector only.
6+
// Reference: Chromium zlib adler32_simd.c, HashLib Adler32BlocksSsse3_x86_64.inc.
7+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
168
// Register map:
179
// w9 = block counter (from w1)
1810
// w10 = SumA in / SumA out

‎HashLib/src/Include/Simd/Argon2/Argon2FillBlockNeon_aarch64.inc‎

Lines changed: 6 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,31 +1,11 @@
1-
// AArch64 NEON implementation of Argon2 FillBlock (BlaMka round function).
2-
//
3-
// Reference: jedisct1/libsodium crypto_pwhash/argon2/argon2-fill-block-neon.c,
4-
// crypto_pwhash/argon2/blamka-round-neon.h; HashLib Argon2FillBlockSse2_x86_64.inc.
5-
//
1+
// Argon2 FillBlock AArch64 NEON implementation (BlaMka round function).
62
// Expects AAPCS64: x0 = Left ptr, x1 = Right ptr, x2 = Current ptr, w3 = WithXor.
73
// Each pointer addresses 128 UInt64 (1024 bytes).
8-
// Uses v0-v7 (A/B/C/D pairs), v16-v18 temps; caller-saved only, leaf nostackframe.
9-
// Stack: 2128 bytes — R_buf at [sp+64], Z_buf at [sp+1088], plus 16-byte SP pad.
10-
// x9 = R_buf, x11 = Z_buf during rounds; x2/w3 survive all loops.
11-
//
12-
// Steps (same semantics as SSE2):
13-
// 1. R_buf = Left XOR Right
14-
// 2. Z_buf = copy(R_buf)
15-
// 3. Eight column rounds on Z_buf (128-byte slices)
16-
// 4. Eight row rounds on Z_buf (stride-16 qword access)
17-
// 5. Current = R_buf XOR Z_buf [XOR Current if WithXor <> 0]
18-
// Indexed loads/stores in steps 1/2/5: ldr/str qN, [xBase, x10].
19-
// Column/row slices: x12 = x11 + x10, then ldr/str qN, [x12, #imm].
20-
// Diagonalize uses vext #8 (blamka-round-neon.h), not SSE2 shufpd.
21-
//
22-
// Instruction encodings (for assembler compatibility):
23-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
24-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
25-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
26-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only
27-
// add/mov/cmp/sub/cbz/b.lo/b/ret stay as text (never ldr/str/ldp with qN).
28-
//
4+
// Stack frame 2128 bytes; see register map.
5+
// Steps: R=Left XOR Right; Z=copy(R); 8 column + 8 row BlaMka rounds on Z;
6+
// Current = R XOR Z [XOR Current if WithXor]. Diagonalize via vext #8.
7+
// Reference: jedisct1/libsodium argon2-fill-block-neon.c, HashLib Argon2FillBlockSse2_x86_64.inc.
8+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
299
// Register map:
3010
// v0-v1 = A0, A1
3111
// v2-v3 = B0, B1

‎HashLib/src/Include/Simd/Blake2B/Blake2BCompressNeon_aarch64.inc‎

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,9 @@
1-
// BLAKE2b AArch64 NEON implementation.
1+
// BLAKE2b compress AArch64 NEON implementation.
22
// Expects AAPCS64: x0 = state ptr (8 x UInt64), x1 = message ptr (128 bytes),
33
// x2 = counter+flags ptr (32 bytes: t[0..1], f[0..1]), x3 = IV ptr (8 x UInt64).
4-
// Touches only caller-saved registers (x0-x3, v0-v7, v16-v19, v20-v23); no AAPCS64
5-
// callee-saved register (x19-x28, or the low 64 bits of v8-v15) is used, so
6-
// the 'nostackframe' leaf needs neither prologue nor epilogue.
7-
// Reference: BLAKE2/BLAKE2 neon/blake2b-neon.c; HashLib Blake2BCompressSse2_x86_64.inc.
8-
//
9-
// Instruction encodings (for assembler compatibility):
10-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
11-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
12-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
13-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only ret
14-
// stays as text.
15-
//
4+
// Leaf nostackframe; uses v8-v15 for message block (d8-d15 lanes; no save/restore).
5+
// Reference: BLAKE2/BLAKE2 neon/blake2b-neon.c, HashLib Blake2BCompressSse2_x86_64.inc.
6+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
167
// Register map:
178
// v0, v1 = row1l, row1h (h[0..3] working, 2 x u64 each)
189
// v2, v3 = row2l, row2h (h[4..7] working)
@@ -22,7 +13,7 @@
2213
// v16-v19 = saved initial row1l/h, row2l/h for the final feed-forward XOR
2314
// v20 = message gather temp b0 (G function)
2415
// v21-v23 = rotate / diagonalize temps (b1 gather uses v23)
25-
// u64 ror-by-32 uses rev64.4s (vrev64q_u32), matching blake2b-neon.c — not rev64.16b.
16+
// u64 ror-by-32 uses rev64.4s (vrev64q_u32), not rev64.16b.
2617

2718
.long 0xad400400 // ldp q0, q1, [x0]
2819
.long 0xad410c02 // ldp q2, q3, [x0, #32]

‎HashLib/src/Include/Simd/Blake2S/Blake2SCompressNeon_aarch64.inc‎

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,9 @@
1-
// BLAKE2s AArch64 NEON implementation.
1+
// BLAKE2s compress AArch64 NEON implementation.
22
// Expects AAPCS64: x0 = state ptr (8 x UInt32), x1 = message ptr (64 bytes),
33
// x2 = counter+flags ptr (16 bytes: t[0..1], f[0..1]), x3 = IV ptr (8 x UInt32).
4-
// Touches only caller-saved registers (x0-x3, v0-v7, v16-v17, v20-v23); no AAPCS64
5-
// callee-saved register (x19-x28, or the low 64 bits of v8-v15) is used, so
6-
// the 'nostackframe' leaf needs neither prologue nor epilogue.
7-
// Reference: BLAKE2/BLAKE2 neon/blake2s-neon.c; HashLib Blake2SCompressSse2_x86_64.inc.
8-
//
9-
// Instruction encodings (for assembler compatibility):
10-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
11-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
12-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
13-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only ret
14-
// stays as text.
15-
//
4+
// Leaf nostackframe; caller-saved GPR/vector only.
5+
// Reference: BLAKE2/BLAKE2 neon/blake2s-neon.c, HashLib Blake2SCompressSse2_x86_64.inc.
6+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
167
// Register map:
178
// v0 = row1 (h[0..3] working)
189
// v1 = row2 (h[4..7] working)

‎HashLib/src/Include/Simd/Blake3/Blake3CompressNeon_aarch64.inc‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,9 @@
11
// BLAKE3 compress AArch64 NEON implementation.
22
// Expects AAPCS64: x0 = state ptr (16 x UInt32), x1 = message ptr (64 bytes),
33
// x2 = CV ptr (8 x UInt32), x3 = counter+flags ptr (16 bytes: t[0..1], len, flags).
4-
// Reference (golden): HashLib Blake3CompressSse2_x86_64.inc (inter-round permute via
5-
// SSE shufps/pshufd semantics); BLAKE3-team/BLAKE3 c/blake3_impl.h (round G / IV).
6-
// Upstream blake3_neon.c has no NEON compress — uses portable C instead.
7-
//
8-
// Instruction encodings (for assembler compatibility):
9-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
10-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
11-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
12-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only
13-
// mov/sub/cbz/ret stay as text.
14-
//
4+
// Stack frame 128 bytes; see register map.
5+
// Reference: BLAKE3-team/BLAKE3 c/blake3_impl.h, HashLib Blake3CompressSse2_x86_64.inc.
6+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
157
// Register map:
168
// v0 = a (v[0..3])
179
// v1 = b (v[4..7])

‎HashLib/src/Include/Simd/Blake3/Blake3Hash4Neon_aarch64.inc‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,10 @@
11
// BLAKE3 hash4 AArch64 NEON implementation (4 parallel 1 KiB chunks).
22
// Expects AAPCS64: x0 = AInput, x1 = AKey, x2 = AOut,
33
// w3 = ANumChunks (unused; always 16 blocks like SSE2), x4 = ACounter, w5 = AFlags.
4-
// Reference (golden): HashLib Blake3Hash4Sse2_x86_64.inc (stack layout, msg indexing,
5-
// output transpose / store offsets); BLAKE3-team/BLAKE3 c/blake3_impl.h (round_fn4,
6-
// MSG_SCHEDULE); scripts/ref/blake3_neon.c (transpose_vecs_128 / round_fn4 structure).
7-
// Output chunk order matches HashLib SSE2, not upstream blake3_neon.c store layout.
8-
//
9-
// Instruction encodings (for assembler compatibility):
10-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector mnemonics
11-
// (subscripted vector regs require FPC 3.3+, and ldr/str/ldp with qN crash the
12-
// 3.2.2 assembler). Each such instruction is therefore emitted as its raw 32-bit
13-
// '.long' opcode, with the equivalent mnemonic in the trailing comment; only
14-
// mov/cmp/sub/cbz/cbnz/b.ne/ret stay as text.
15-
//
4+
// Stack frame 720 bytes; see register map.
5+
// Reference: BLAKE3-team/BLAKE3 c/blake3_impl.h, HashLib Blake3Hash4Sse2_x86_64.inc
6+
// (output chunk order matches HashLib SSE2, not upstream blake3_neon.c store layout).
7+
// AArch64 vector instructions are .long-encoded for broad assembler compatibility.
168
// Register map:
179
// v0-v7 = state v0..v7 (CV rows, 4-wide)
1810
// v8-v11 = state v8..v11 (IV rows, updated each round)

‎HashLib/src/Include/Simd/SHA1/SHA1CompressCryptoExt_aarch64.inc‎

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,9 @@
1-
// SHA-1 ARMv8 Crypto Extension (FEAT_SHA1) implementation.
1+
// SHA-1 AArch64 FEAT_SHA1 implementation.
22
// Expects AAPCS64: x0 = state ptr (5 x UInt32), x1 = data ptr,
3-
// w2 = numblocks, x3 = K_SHA1 ptr (16 UInt32: each of the four round
4-
// constants replicated across 4 lanes).
5-
// Touches only caller-saved registers (x0-x3, w2, v0-v7, v16-v22); no AAPCS64
6-
// callee-saved register (x19-x28, or the low 64 bits of v8-v15) is used, so
7-
// the 'nostackframe' leaf needs neither prologue nor epilogue.
8-
// Reference: OpenSSL CRYPTOGAMS sha1-armv8.S (sha1_block_armv8).
9-
//
10-
// Instruction encodings (for assembler compatibility):
11-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector/crypto mnemonics
12-
// (subscripted vector regs and the FEAT_SHA1 ops require FPC 3.3+, and
13-
// ldr/str/ldp with qN/sN crash the 3.2.2 assembler). Each such instruction is
14-
// therefore emitted as its raw 32-bit '.long' opcode, with the equivalent
15-
// mnemonic in the trailing comment; only cbz/cbnz/sub/ret stay as text.
16-
//
3+
// w2 = numblocks, x3 = K_SHA1 ptr (16 UInt32: each round constant x4 lanes).
4+
// Leaf nostackframe; caller-saved GPR/vector only.
5+
// Reference: OpenSSL CRYPTOGAMS sha1-armv8.S, HashLib SHA1CompressSse2_x86_64.inc.
6+
// AArch64 vector/crypto instructions are .long-encoded for broad assembler compatibility.
177
// Register map:
188
// v0 = ABCD working state
199
// v1.s[0] = E working state (single lane; sha1c/p/m consume it as a scalar)

‎HashLib/src/Include/Simd/SHA256/SHA256CompressCryptoExt_aarch64.inc‎

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,10 @@
1-
// SHA-256 ARMv8 Crypto Extension (FEAT_SHA256) implementation.
1+
// SHA-256 AArch64 FEAT_SHA256 implementation.
22
// Expects AAPCS64: x0 = state ptr (8 x UInt32), x1 = data ptr,
33
// w2 = numblocks, x3 = K256 ptr (64 UInt32 round constants).
4-
// Touches only caller-saved registers (x0-x4, w2, v0-v7, v16-v19); no AAPCS64
5-
// callee-saved register (x19-x28, or the low 64 bits of v8-v15) is used, so
6-
// the 'nostackframe' leaf needs neither prologue nor epilogue. The K pointer
7-
// is advanced with post-index loads and rewound once per block with
8-
// 'sub x3,x3,#240' (= 64*4 - 16), avoiding the need for a saved base register.
9-
// Reference: OpenSSL CRYPTOGAMS sha256-armv8.S (sha256_block_armv8).
10-
//
11-
// Instruction encodings (for assembler compatibility):
12-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector/crypto mnemonics
13-
// (subscripted vector regs and the FEAT_SHA256 ops require FPC 3.3+, and
14-
// ldr/str/ldp with qN crash the 3.2.2 assembler). Each such instruction is
15-
// therefore emitted as its raw 32-bit '.long' opcode, with the equivalent
16-
// mnemonic in the trailing comment; only cbz/cbnz/sub/ret stay as text.
17-
//
4+
// Leaf nostackframe; caller-saved GPR/vector only.
5+
// K pointer rewound each block (sub x3, #240) after post-index loads.
6+
// Reference: OpenSSL CRYPTOGAMS sha256-armv8.S, HashLib SHA256CompressSse2_x86_64.inc.
7+
// AArch64 vector/crypto instructions are .long-encoded for broad assembler compatibility.
188
// Register map:
199
// v0, v1 = working state (ABCD, EFGH)
2010
// v2 = sha256h2 temp (copy of v0 before each h/h2 pair)

‎HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExtAbsorb_aarch64.inc‎

Lines changed: 7 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,13 @@
1-
// SHA-3 (Keccak-F1600) ARMv8 Crypto Extension (FEAT_SHA3) sponge absorb.
1+
// Keccak-F1600 absorb AArch64 FEAT_SHA3 implementation.
22
// Expects AAPCS64: x0 = state ptr (25 x UInt64), x1 = data ptr,
33
// w2 = numblocks, w3 = blocksize (bytes, = rate), x4 = iotas ptr.
4-
// For each block it XORs blocksize bytes (per 64-bit lane, little-endian)
5-
// into the low lanes and runs the inlined 24-round permutation, resetting
6-
// the iota pointer (x4 -> x10) before every permute. The per-lane
7-
// cmp/b.lo/b.eq dispatch mirrors OpenSSL so any rate <= 200 bytes works;
8-
// the outer loop counts blocks (HlpSHA3 contract) rather than byte length.
9-
// v8-v15 (callee-saved d8-d15) are saved/restored; still a leaf (no calls).
10-
// Reference: OpenSSL CRYPTOGAMS keccak1600-armv8.S (SHA3_absorb_cext).
11-
//
12-
// Instruction encodings (for assembler compatibility):
13-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector/crypto mnemonics
14-
// (subscripted vector regs and the FEAT_SHA3 ops require FPC 3.3+, and
15-
// ldp/stp/ldr/str with dN crash the 3.2.2 assembler). Each such instruction
16-
// is emitted as its raw 32-bit '.long' opcode, with the equivalent mnemonic
17-
// in the trailing comment; only mov/cmp/sub/cbz/cbnz/b.lo/b.eq/ret stay as
18-
// text.
19-
//
4+
// Saves/restores d8-d15 on 64-byte frame; XORs blocksize bytes per block then permutes.
5+
// Reference: OpenSSL CRYPTOGAMS keccak1600-armv8.S, HashLib KeccakF1600Avx2Absorb_x86_64.inc.
6+
// AArch64 vector/crypto instructions are .long-encoded for broad assembler compatibility.
207
// Register map:
21-
// v0-v24 = Keccak state lanes (data is XORed lane-by-lane into v0..)
22-
// v25-v31 = permutation scratch; v31 also holds each loaded input lane
8+
// v0-v24 = Keccak state lanes (data XORed lane-by-lane into v0..)
9+
// v25-v30 = permutation scratch
10+
// v31 = loaded input lane
2311

2412
.long 0x6dbc27e8 // stp d8, d9, [sp, #-64]!
2513
.long 0x6d012fea // stp d10, d11, [sp, #16]

‎HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExt_aarch64.inc‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,15 @@
1-
// SHA-3 (Keccak-F1600) ARMv8 Crypto Extension (FEAT_SHA3) permutation.
1+
// Keccak-F1600 permute AArch64 FEAT_SHA3 implementation.
22
// Expects AAPCS64: x0 = state ptr (25 x UInt64, little-endian lanes),
33
// x1 = iotas ptr (24 x UInt64 round constants == HlpSHA3 RC table).
4-
// The 25 lanes occupy v0-v24, so the low 64 bits of v8-v15 (AAPCS64
5-
// callee-saved d8-d15) are clobbered; the prologue/epilogue saves and
6-
// restores them on a 64-byte frame. The permute loop is inlined (no calls)
7-
// so the routine is still a leaf and x30 is untouched.
8-
// Reference: OpenSSL CRYPTOGAMS keccak1600-armv8.S (KeccakF1600_ce loop).
9-
//
10-
// Instruction encodings (for assembler compatibility):
11-
// FPC 3.2.2's inline assembler cannot encode AArch64 vector/crypto mnemonics
12-
// (subscripted vector regs and the FEAT_SHA3 ops require FPC 3.3+, and
13-
// ldp/stp/ldr/str with dN crash the 3.2.2 assembler). Each such instruction
14-
// is emitted as its raw 32-bit '.long' opcode, with the equivalent mnemonic
15-
// in the trailing comment; only mov/sub/cbnz/ret stay as text.
16-
//
4+
// Saves/restores d8-d15 on 64-byte frame; state uses v0-v24 (clobbers d8-d15 lanes).
5+
// Leaf (no calls); x30 untouched.
6+
// Reference: OpenSSL CRYPTOGAMS keccak1600-armv8.S, HashLib KeccakF1600Avx2_x86_64.inc.
7+
// AArch64 vector/crypto instructions are .long-encoded for broad assembler compatibility.
178
// Register map:
189
// v0-v24 = Keccak state lanes A[y][x] (lane k = v[k], 64 bits in low half)
19-
// v25-v29 = Theta C[]/D[] column and Rho/Pi scratch
20-
// v26 = iota round constant (ld1r), v30, v31 = Rho/Pi scratch
10+
// v25-v29 = Theta C[]/D[] column scratch
11+
// v26 = iota round constant (ld1r)
12+
// v30-v31 = Rho/Pi scratch
2113

2214
.long 0x6dbc27e8 // stp d8, d9, [sp, #-64]!
2315
.long 0x6d012fea // stp d10, d11, [sp, #16]

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