Skip to content

Commit e8f8297

Browse files
jixjix
authored
Merge pull request #5376 from rocallahan/remove-more-cstr
Remove more uses of `.c_str()`
2 parents cb9d0b6 + 1e5f920 commit e8f8297

File tree

17 files changed

+67
-67
lines changed

17 files changed

+67
-67
lines changed

‎backends/aiger2/aiger.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1017,7 +1017,7 @@ struct XAigerWriter : AigerWriter {
10171017
auto &minfo = cursor.leaf_minfo(*this);
10181018

10191019
for (auto box : minfo.found_blackboxes) {
1020-
log_debug(" - %s.%s (type %s): ", cursor.path().c_str(),
1020+
log_debug(" - %s.%s (type %s): ", cursor.path(),
10211021
RTLIL::unescape_id(box->name),
10221022
log_id(box->type));
10231023

‎frontends/aiger/aigerparse.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -476,7 +476,7 @@ void AigerReader::parse_xaiger()
476476
else if (c == 'n') {
477477
parse_xaiger_literal(f);
478478
f >> s;
479-
log_debug("n: '%s'\n", s.c_str());
479+
log_debug("n: '%s'\n", s);
480480
}
481481
else if (c == 'h') {
482482
f.ignore(sizeof(uint32_t));

‎frontends/rpc/rpc_frontend.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,11 +83,11 @@ struct RpcServer {
8383
std::string request;
8484
json_request.dump(request);
8585
request += '\n';
86-
log_debug("RPC frontend request: %s", request.c_str());
86+
log_debug("RPC frontend request: %s", request);
8787
write(request);
8888

8989
std::string response = read();
90-
log_debug("RPC frontend response: %s", response.c_str());
90+
log_debug("RPC frontend response: %s", response);
9191
std::string error;
9292
Json json_response = Json::parse(response, error);
9393
if (json_response.is_null())

‎kernel/cost.cc‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -143,14 +143,14 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
143143
return 1;
144144

145145
if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
146-
log_debug("%s is a module, recurse\n", cell->name.c_str());
146+
log_debug("%s is a module, recurse\n", cell->name);
147147
return get(design_->module(cell->type));
148148
} else if (cell->is_builtin_ff()) {
149149
log_assert(cell->hasPort(ID::Q) && "Weird flip flop");
150-
log_debug("%s is ff\n", cell->name.c_str());
150+
log_debug("%s is ff\n", cell->name);
151151
return cell->getParam(ID::WIDTH).as_int();
152152
} else if (cell->type.in(ID($mem), ID($mem_v2))) {
153-
log_debug("%s is mem\n", cell->name.c_str());
153+
log_debug("%s is mem\n", cell->name);
154154
return cell->getParam(ID::WIDTH).as_int() * cell->getParam(ID::SIZE).as_int();
155155
} else if (y_coef(cell->type)) {
156156
// linear with Y_WIDTH or WIDTH
@@ -159,23 +159,23 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
159159
int width = cell->getParam(param).as_int();
160160
if (cell->type == ID($demux))
161161
width <<= cell->getParam(ID::S_WIDTH).as_int();
162-
log_debug("%s Y*coef %d * %d\n", cell->name.c_str(), width, y_coef(cell->type));
162+
log_debug("%s Y*coef %d * %d\n", cell->name, width, y_coef(cell->type));
163163
return width * y_coef(cell->type);
164164
} else if (sum_coef(cell->type)) {
165165
// linear with sum of port widths
166166
unsigned int sum = port_width_sum(cell);
167-
log_debug("%s sum*coef %d * %d\n", cell->name.c_str(), sum, sum_coef(cell->type));
167+
log_debug("%s sum*coef %d * %d\n", cell->name, sum, sum_coef(cell->type));
168168
return sum * sum_coef(cell->type);
169169
} else if (max_inp_coef(cell->type)) {
170170
// linear with largest input width
171171
unsigned int max = max_inp_width(cell);
172-
log_debug("%s max*coef %d * %d\n", cell->name.c_str(), max, max_inp_coef(cell->type));
172+
log_debug("%s max*coef %d * %d\n", cell->name, max, max_inp_coef(cell->type));
173173
return max * max_inp_coef(cell->type);
174174
} else if (is_div_mod(cell->type) || cell->type == ID($mul)) {
175175
// quadratic with sum of port widths
176176
unsigned int sum = port_width_sum(cell);
177177
unsigned int coef = cell->type == ID($mul) ? 3 : 5;
178-
log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum);
178+
log_debug("%s coef*(sum**2) %d * %d\n", cell->name, coef, sum * sum);
179179
return coef * sum * sum;
180180
} else if (cell->type.in(ID($macc), ID($macc_v2))) {
181181
// quadratic per term
@@ -196,15 +196,15 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
196196
} else if (cell->type == ID($lut)) {
197197
int width = cell->getParam(ID::WIDTH).as_int();
198198
unsigned int cost = 1U << (unsigned int)width;
199-
log_debug("%s is 2**%d\n", cell->name.c_str(), width);
199+
log_debug("%s is 2**%d\n", cell->name, width);
200200
return cost;
201201
} else if (cell->type == ID($sop)) {
202202
int width = cell->getParam(ID::WIDTH).as_int();
203203
int depth = cell->getParam(ID::DEPTH).as_int();
204-
log_debug("%s is (2*%d + 1)*%d\n", cell->name.c_str(), width, depth);
204+
log_debug("%s is (2*%d + 1)*%d\n", cell->name, width, depth);
205205
return (2 * width + 1) * depth;
206206
} else if (is_free(cell->type)) {
207-
log_debug("%s is free\n", cell->name.c_str());
207+
log_debug("%s is free\n", cell->name);
208208
return 0;
209209
}
210210
// TODO: $fsm

‎kernel/fstdata.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ void FstData::extractVarNames()
162162
char *endptr;
163163
int mem_addr = strtol(addr.c_str(), &endptr, 16);
164164
if (*endptr) {
165-
log_debug("Error parsing memory address in : %s\n", clean_name.c_str());
165+
log_debug("Error parsing memory address in : %s\n", clean_name);
166166
} else {
167167
memory_to_handle[var.scope+"."+mem_cell][mem_addr] = var.id;
168168
}
@@ -176,7 +176,7 @@ void FstData::extractVarNames()
176176
char *endptr;
177177
int mem_addr = strtol(addr.c_str(), &endptr, 10);
178178
if (*endptr) {
179-
log_debug("Error parsing memory address in : %s\n", clean_name.c_str());
179+
log_debug("Error parsing memory address in : %s\n", clean_name);
180180
} else {
181181
memory_to_handle[var.scope+"."+mem_cell][mem_addr] = var.id;
182182
}

‎passes/cmds/abstract.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,9 +156,9 @@ dict<SigBit, std::vector<SelReason>> gather_selected_reps(Module* mod, const std
156156
void explain_selections(const std::vector<SelReason>& reasons) {
157157
for (std::variant<Wire*, Cell*> reason : reasons) {
158158
if (Cell** cell_reason = std::get_if<Cell*>(&reason))
159-
log_debug("\tcell %s\n", (*cell_reason)->name.c_str());
159+
log_debug("\tcell %s\n", (*cell_reason)->name);
160160
else if (Wire** wire_reason = std::get_if<Wire*>(&reason))
161-
log_debug("\twire %s\n", (*wire_reason)->name.c_str());
161+
log_debug("\twire %s\n", (*wire_reason)->name);
162162
else
163163
log_assert(false && "insane reason variant\n");
164164
}

‎passes/cmds/box_derive.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ struct BoxDerivePass : Pass {
9696
IdString derived_type = base->derive(d, cell->parameters);
9797
Module *derived = d->module(derived_type);
9898
log_assert(derived && "Failed to derive module\n");
99-
log_debug("derived %s\n", derived_type.c_str());
99+
log_debug("derived %s\n", derived_type);
100100

101101
if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
102102
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));

‎passes/cmds/linecoverage.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ struct CoveragePass : public Pass {
9595
{
9696
log_debug("Module %s:\n", log_id(module));
9797
for (auto wire: module->wires()) {
98-
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute().c_str(), log_id(wire->name));
98+
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), log_id(wire->name));
9999
for (auto src: wire->get_strpool_attribute(ID::src)) {
100100
auto filename = extract_src_filename(src);
101101
if (filename.empty()) continue;
@@ -109,7 +109,7 @@ struct CoveragePass : public Pass {
109109
}
110110
}
111111
for (auto cell: module->cells()) {
112-
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute().c_str(), log_id(cell->name));
112+
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), log_id(cell->name));
113113
for (auto src: cell->get_strpool_attribute(ID::src)) {
114114
auto filename = extract_src_filename(src);
115115
if (filename.empty()) continue;

‎passes/memory/memory_libmap.cc‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -392,7 +392,7 @@ void MemMapping::dump_configs(int stage) {
392392
void MemMapping::dump_config(MemConfig &cfg) {
393393
log_debug("- %s:\n", log_id(cfg.def->id));
394394
for (auto &it: cfg.def->options)
395-
log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second));
395+
log_debug(" - option %s %s\n", it.first, log_const(it.second));
396396
log_debug(" - emulation score: %d\n", cfg.score_emu);
397397
log_debug(" - replicates (for ports): %d\n", cfg.repl_port);
398398
log_debug(" - replicates (for data): %d\n", cfg.repl_d);
@@ -403,7 +403,7 @@ void MemMapping::dump_config(MemConfig &cfg) {
403403
for (int x: cfg.def->dbits)
404404
os << " " << x;
405405
std::string dbits_s = os.str();
406-
log_debug(" - abits %d dbits%s\n", cfg.def->abits, dbits_s.c_str());
406+
log_debug(" - abits %d dbits%s\n", cfg.def->abits, dbits_s);
407407
if (cfg.def->byte != 0)
408408
log_debug(" - byte width %d\n", cfg.def->byte);
409409
log_debug(" - chosen base width %d\n", cfg.def->dbits[cfg.base_width_log2]);
@@ -414,25 +414,25 @@ void MemMapping::dump_config(MemConfig &cfg) {
414414
else
415415
os << " " << x;
416416
std::string swizzle_s = os.str();
417-
log_debug(" - swizzle%s\n", swizzle_s.c_str());
417+
log_debug(" - swizzle%s\n", swizzle_s);
418418
os.str("");
419419
for (int i = 0; (1 << i) <= cfg.hard_wide_mask; i++)
420420
if (cfg.hard_wide_mask & 1 << i)
421421
os << " " << i;
422422
std::string wide_s = os.str();
423423
if (cfg.hard_wide_mask)
424-
log_debug(" - hard wide bits%s\n", wide_s.c_str());
424+
log_debug(" - hard wide bits%s\n", wide_s);
425425
if (cfg.emu_read_first)
426426
log_debug(" - emulate read-first behavior\n");
427427
for (int i = 0; i < GetSize(mem.wr_ports); i++) {
428428
auto &pcfg = cfg.wr_ports[i];
429429
if (pcfg.rd_port == -1)
430-
log_debug(" - write port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str());
430+
log_debug(" - write port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0]);
431431
else
432-
log_debug(" - write port %d: port group %s (shared with read port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.rd_port);
432+
log_debug(" - write port %d: port group %s (shared with read port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0], pcfg.rd_port);
433433

434434
for (auto &it: pcfg.def->options)
435-
log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second));
435+
log_debug(" - option %s %s\n", it.first, log_const(it.second));
436436
if (cfg.def->width_mode == WidthMode::PerPort) {
437437
std::stringstream os;
438438
for (int i = pcfg.def->min_wr_wide_log2; i <= pcfg.def->max_wr_wide_log2; i++)
@@ -441,19 +441,19 @@ void MemMapping::dump_config(MemConfig &cfg) {
441441
const char *note = "";
442442
if (pcfg.rd_port != -1)
443443
note = pcfg.def->width_tied ? " (tied)" : " (independent)";
444-
log_debug(" - widths%s%s\n", widths_s.c_str(), note);
444+
log_debug(" - widths%s%s\n", widths_s, note);
445445
}
446446
for (auto i: pcfg.emu_prio)
447447
log_debug(" - emulate priority over write port %d\n", i);
448448
}
449449
for (int i = 0; i < GetSize(mem.rd_ports); i++) {
450450
auto &pcfg = cfg.rd_ports[i];
451451
if (pcfg.wr_port == -1)
452-
log_debug(" - read port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str());
452+
log_debug(" - read port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0]);
453453
else
454-
log_debug(" - read port %d: port group %s (shared with write port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.wr_port);
454+
log_debug(" - read port %d: port group %s (shared with write port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0], pcfg.wr_port);
455455
for (auto &it: pcfg.def->options)
456-
log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second));
456+
log_debug(" - option %s %s\n", it.first, log_const(it.second));
457457
if (cfg.def->width_mode == WidthMode::PerPort) {
458458
std::stringstream os;
459459
for (int i = pcfg.def->min_rd_wide_log2; i <= pcfg.def->max_rd_wide_log2; i++)
@@ -462,7 +462,7 @@ void MemMapping::dump_config(MemConfig &cfg) {
462462
const char *note = "";
463463
if (pcfg.wr_port != -1)
464464
note = pcfg.def->width_tied ? " (tied)" : " (independent)";
465-
log_debug(" - widths%s%s\n", widths_s.c_str(), note);
465+
log_debug(" - widths%s%s\n", widths_s, note);
466466
}
467467
if (pcfg.emu_sync)
468468
log_debug(" - emulate data register\n");
@@ -2242,7 +2242,7 @@ struct MemoryLibMapPass : public Pass {
22422242
if (!map.logic_ok) {
22432243
if (map.cfgs.empty()) {
22442244
log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module->name), log_id(mem.memid));
2245-
log_debug("%s", map.rejected_cfg_debug_msgs.c_str());
2245+
log_debug("%s", map.rejected_cfg_debug_msgs);
22462246
log_error("no valid mapping found for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
22472247
}
22482248
idx = 0;

‎passes/opt/opt_clean.cc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ void rmunused_module_cells(Module *module, bool verbose)
204204

205205
for (auto cell : unused) {
206206
if (verbose)
207-
log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
207+
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
208208
module->design->scratchpad_set_bool("opt.did_something", true);
209209
if (cell->is_builtin_ff())
210210
ffinit.remove_init(cell->getPort(ID::Q));
@@ -215,7 +215,7 @@ void rmunused_module_cells(Module *module, bool verbose)
215215
for (auto it : mem_unused)
216216
{
217217
if (verbose)
218-
log_debug(" removing unused memory `%s'.\n", it.c_str());
218+
log_debug(" removing unused memory `%s'.\n", it);
219219
delete module->memories.at(it);
220220
module->memories.erase(it);
221221
}
@@ -496,7 +496,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
496496
int del_temp_wires_count = 0;
497497
for (auto wire : del_wires_queue) {
498498
if (ys_debug() || (check_public_name(wire->name) && verbose))
499-
log_debug(" removing unused non-port wire %s.\n", wire->name.c_str());
499+
log_debug(" removing unused non-port wire %s.\n", wire->name);
500500
else
501501
del_temp_wires_count++;
502502
}
@@ -636,7 +636,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
636636
}
637637
for (auto cell : delcells) {
638638
if (verbose)
639-
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
639+
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
640640
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
641641
module->remove(cell);
642642
}

0 commit comments

Comments
 (0)