Open
Description
Version
Yosys 0.44 (git sha1 80ba43d, clang++-18 18.1.8 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
module test(in1, in2, out1);
input in1, in2;
output out1;
nand #2 t_nand[0:7](out1, in1, in2);
nand #2 x_nand[0:3](out1, in1, in2), y_nand[4:7](out1, in1, in2);
endmoduleExpected Behavior
IEEE Std 1364-2005:
7. Gate- and switch-level modeling
7.1 Gate and switch declaration syntax
7.1.5 The range specification
An array of instances shall have a continuous range. One instance identifier shall be
associated with only one range to declare an array of instances.
The range specification shall be optional. If no range specification is given, a single
instance shall be created.
The module body specified in reproduction steps was taken directly from the standard (page 78). It should be parsed just fine.
Actual Behavior
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2024 Claire Xenia Wolf <[email protected]> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.44 (git sha1 80ba43d26, clang++-18 18.1.8 -fPIC -O3)
yosys> read_verilog module.v
1. Executing Verilog-2005 frontend: module.v
Parsing Verilog input from `module.v' to AST representation.
Generating RTLIL representation for module `\test'.
ERROR: Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2686.