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std::out_of_range during write_aiger #5097

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@nblei

Description

@nblei

Version

Yosys 0.44 (git sha1 80ba43d, g++ 14.2.0-4ubuntu2~24.04 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

$ yosys -s syn.txt

syn.txt

read_verilog -sv ../sources_1/new/*.sv
hierarchy -check -top Datapath
proc; opt; fsm; opt; memory; opt
techmap;
async2sync;
opt; flatten;
alumacc; dffunmap; aigmap; opt;

write_aiger -zinit -symbols -vmap datapath.aim datapath.aig

verilog is from: https://github.com/martinKindall/risc-v-single-cycle commit 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4

git clone --depth 1 https://github.com/martinKindall/risc-v-single-cycle commit temp_dir
cd temp_dir
git fetch --depth 1 origin 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4
git checkout 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4
mkdir syn
cd syn
echo "read_verilog -sv ../sources_1/new/*.sv \
                                                    hierarchy -check -top Datapath \
                                                    proc; opt; fsm; opt; memory; opt \
                                                    techmap; \
                                                    async2sync; \
                                                    opt; flatten; \
                                                    alumacc; dffunmap; aigmap; opt;\ 
                                                    write_aiger -zinit -symbols -vmap datapath.aim datapath.aig \
                                                    " > syn.txt
yosys -s syn.txt

Expected Behavior

Export and-inverter graph and mapping files, or report error.

Actual Behavior

uncaught std::out_of_range exception.

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