setundef causes conflicts when applied to undriven signals with init #5835

Version

Yosys 0.64+149 (git sha1 2dc69a7, ccache clang++ 18.1.3 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Run the following script with Yosys

read_rtlil << EOT
module \top
    attribute \init 3
    wire width 4 \i
end
EOT
setundef -undriven -undef
opt

Note that this was discovered while preparing a design for use with write_functional_rosette where the original script was more along the lines of

# read design
prep -flatten
clk2fflogic
setundef -undriven -undef
opt -fast
write_functional_rosette out.rkt

Expected Behavior

setundef -undriven should either ignore wires with an init attribute, remove the init attribute, or raise an error/warning that it is unsupported.

Actual Behavior

The call to setundef produces

module \top

  attribute \init 3
  wire width 4 \i

  connect \i 4'x
end

which then gives the following error

3.2. Executing OPT_MERGE pass (detect identical cells).
ERROR: Conflicting init values for signal 1'x (\i [2] = 1'0 != 1'1).

I thought that setundef -undriven -undef -init might make a difference, but -init and -undriven are non overlapping (since -init looks for ffs driving a wire to move the init attribute, but if it's -undriven then there must not be an ff). init attributes confuse me... maybe we should have a docs page about them and how they are expected to work.

Using a version of Yosys with #5724 (e.g v0.64) offers the workaround of setundef -undriven -undef a:init %n which bypasses the error and resolves the issue (at least for use with write_functional_rosette), but I'm not 100% confident that is true for all cases.