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samples: boards: nxp: add mimxrt700_evk dual_core_pm sample
Add a dual-core power management sample for the MIMXRT700-EVK. Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
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‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/CMakeLists.txt‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(rt700_dual_core_pm)
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if(NOT CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0)
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message(FATAL_ERROR "${BOARD}/${BOARD_QUALIFIERS} is not supported by this sample")
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endif()
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if(CONFIG_INCLUDE_REMOTE_DIR)
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target_include_directories(zephyr_interface
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INTERFACE ${REMOTE_ZEPHYR_DIR}/include/public)
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endif()
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target_sources(app PRIVATE src/main.c)
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target_include_directories(app PRIVATE
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${ZEPHYR_BASE}/../modules/hal/nxp/mcux/mcux-sdk-ng/drivers/mu1)

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/Kconfig‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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source "Kconfig.zephyr"
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config INCLUDE_REMOTE_DIR
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bool "Include remote core header directory"
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help
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Include remote build header files. The RT700 CPU0 image needs the
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CPU1 image information header when CONFIG_SECOND_CORE_MCUX is enabled.
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config RT700_DUAL_CORE_PM_SLEEP_SECONDS
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int "Power-mode measurement window in seconds"
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default 10
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range 1 3600
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help
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Number of seconds each active, sleep, or deep-sleep test case runs.

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/Kconfig.sysbuild‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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source "share/sysbuild/Kconfig"
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config RT700_DUAL_CORE_PM_REMOTE_BOARD
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string "RT700 dual-core PM remote board"
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default "mimxrt700_evk/mimxrt798s/cm33_cpu1" if $(BOARD) = "mimxrt700_evk"
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help
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Board target used for the CM33 CPU1 remote image.
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config RT700_DUAL_CORE_PM_SLEEP_SECONDS
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int "Power-mode measurement window in seconds"
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default 10
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range 1 3600
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help
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Number of seconds both cores spend in each active, sleep, or
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deep-sleep measurement window.

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/README.rst‎

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.. zephyr:code-sample:: nxp_rt700_dual_core_pm
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:name: RT700 EVK dual-core power management
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Exercise active, sleep, and deep-sleep combinations on both RT700 EVK
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Cortex-M33 cores.
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Overview
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********
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This sample builds two Zephyr images for the MIMXRT700-EVK:
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* the main image runs on CM33 CPU0 and boots CM33 CPU1 through the existing
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``CONFIG_SECOND_CORE_MCUX`` board initialization path;
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* the remote image runs on CM33 CPU1.
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Both images enable Zephyr system power management and register a PM notifier.
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CPU0 acts as the test orchestrator and sends simple MU commands to the CPU1
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remote image. CPU1 acknowledges that it is ready, CPU0 sends a GO command, and
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then both cores run the selected measurement window.
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The test matrix covers:
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* both cores active;
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* CPU0 sleep while CPU1 stays active;
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* CPU1 sleep while CPU0 stays active;
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* both cores sleep;
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* CPU0 deep-sleep while CPU1 stays active;
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* CPU1 deep-sleep while CPU0 stays active;
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* both cores deep-sleep.
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The sleep cases force ``PM_STATE_RUNTIME_IDLE`` for the next idle entry. The
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deep-sleep cases force ``PM_STATE_SUSPEND_TO_IDLE`` for the next idle entry.
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The serial output gives a coarse software confirmation that both cores booted
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and that PM entry/exit callbacks are firing. Use the stable sleep windows for
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board current measurement.
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Building and Running
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********************
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Build the CPU0 and CPU1 images together with sysbuild:
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.. zephyr-app-commands::
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:zephyr-app: samples/boards/nxp/mimxrt700_evk/dual_core_pm
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:board: mimxrt700_evk/mimxrt798s/cm33_cpu0
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:west-args: --sysbuild
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:goals: build flash
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:compact:
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After reset, the console should show CPU0 stepping through the matrix and CPU1
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responding to each command, for example:
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.. code-block:: console
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RT700 dual-core PM sample: CPU0 started on mimxrt700_evk/mimxrt798s/cm33_cpu0
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RT700 dual-core PM sample: CPU1 started on mimxrt700_evk/mimxrt798s/cm33_cpu1
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CPU0: case 1: active baseline
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CPU1: prepared for active window
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CPU0: entering active window
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CPU1: entering active window
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CPU1: active window complete
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CPU0: local active window complete
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CPU0: case 4: CPU0 and CPU1 sleep
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CPU1: prepared for sleep window
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CPU0: entering sleep window
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Measurement Notes
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*****************
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Measure RT700 SoC current through JP21 on the EVK. Remove the default JP21
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jumper and insert the current meter or power analyzer in series. JP21 measures
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the RT700 SoC rail, so it does not isolate CPU0 and CPU1 independently. To see
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the contribution of each core, compare the active baseline, single-core sleep,
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single-core deep-sleep, and coordinated sleep/deep-sleep windows.
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The default low-power window is 10 seconds. It can be changed at build time:
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.. code-block:: console
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west build -p always --sysbuild \
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-b mimxrt700_evk/mimxrt798s/cm33_cpu0 \
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samples/boards/nxp/mimxrt700_evk/dual_core_pm \
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-- -DSB_CONFIG_RT700_DUAL_CORE_PM_SLEEP_SECONDS=30

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SECOND_CORE_MCUX=y
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CONFIG_INCLUDE_REMOTE_DIR=y
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CONFIG_COUNTER=y
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CONFIG_MCUX_OS_TIMER_PM_POWERED_OFF=y

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay‎

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/*
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* Copyright 2026 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* The dual-core PM sample does not use I2C or the on-board PCA9422 PMIC.
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*
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* On CPU0 the LPI2C15 functional clock is sourced from the SENSE domain base
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* clock, which is configured by CPU1 (not CPU0). When the PMIC MFD driver is
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* pulled in it initializes LPI2C15 while its clock rate is still 0, which makes
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* the MCUX LPI2C driver divide by zero during baud-rate setup. Disabling the
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* unused bus (and the PMIC node on it) keeps the sample focused on dual-core
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* power-management coordination over the MU.
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*/
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&lpi2c15 {
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status = "disabled";
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};
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&pca9422 {
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status = "disabled";
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};
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/*
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* In the dual-core PM matrix CPU0 enters deep sleep while CPU1 keeps running
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* (cases 5-7). The default SLEEPCON0 deep-sleep mask gates the SENSE-domain and
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* common main clocks and powers down every oscillator (XTAL, FRO0-2, LPOSC),
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* and the default PDSLEEPCFG2/3 masks power down the SRAM partitions that hold
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* CPU1's code and data (0x5C0000-0x67FFFF). Either one freezes CPU1's core.
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* Override the deep-sleep config so CPU0 deep sleep keeps the clocks and RAM
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* CPU1 depends on alive.
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*
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* deep-sleep-config words map to the SoC power code's excl[] mask (bits to
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* NOT gate / NOT power down):
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* word0 = SLEEPCON0 SLEEPCFG keep-alive (clocks/oscillators)
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* word1 = PDSLEEPCFG0 keep-powered (voltage domains)
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* word2 = PDSLEEPCFG1 keep-powered
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* word3 = PDSLEEPCFG2 keep-powered (SRAM partitions 0-31)
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* word4 = PDSLEEPCFG3 keep-powered (SRAM partitions 32-63)
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* word5 = PDSLEEPCFG4 keep-powered (caches / OTP / peripherals)
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* word6 = PDSLEEPCFG5 keep-powered
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*
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* word0 = 0xA000FFA6 keeps: SENSEP/SENSES/COMN main clocks (bits 1,2,5),
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* XTAL/FRO0-2/LPOSC (bits 7-11), all PLLs (bits 12-15) and the FRO0/FRO2
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* output gates (bits 29,31). word1 = 0x140 keeps VDDN_COM fully powered
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* (VNCOM_DSR bit8 + V2NMED_DSR bit6) so CPU0 resumes in place instead of
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* warm-resetting into ROM. word3/word4 = 0xFFFFFFFF keep all SRAM partitions
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* powered so CPU1's image survives CPU0 deep sleep.
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*/
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&deepsleep {
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deep-sleep-config = <0xa000ffa6 0x140 0x0
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0xffffffff 0xffffffff 0x400c00 0x0>;
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};
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/*
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* Deep sleep retention reuses the same dual-core keep-alive mask as deep sleep
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* (case 8: CPU0 DSR while CPU1 is parked in deep sleep). Full deep-sleep
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* retention (FDSR) is a dual-domain mode: it only engages when both the compute
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* and sense domains request deep sleep. Keeping the SENSE / COMN clocks and all
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* SRAM partitions alive lets both cores resume in place afterwards.
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*
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* word1 = 0x1C0 excludes V2COM_DSR (bit7) in addition to VNCOM_DSR (bit8) and
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* V2NMED_DSR (bit6). PCFG0_DSR requests all three, but V2COM_DSR (the shared
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* VDD2 common rail) must only be retained when *every* VDD2/VDDN companion is
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* also retained (PMC rule: "when V2COM_DSR, other VDD2 and VDDN switches should
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* be off"). Since not every VDD2/VDDN companion enters retention here, V2COM_DSR
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* must be excluded - otherwise the PMC enters an inconsistent retention state,
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* the common VDD2/VDDN rail collapses, and CPU0 warm-resets into the boot ROM
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* instead of resuming in place. Excluding it leaves only V2COMP_DSR (CPU0's own
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* compute logic), which together with the FDSR domain bits is exactly what
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* case 8 needs.
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*/
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&dsr {
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deep-sleep-retention-config = <0xa000ffa6 0x1c0 0x0
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0xffffffff 0xffffffff 0x400c00 0x0>;
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};
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/*
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* In DSR (case 8) the OS Timer that drives the system tick loses power because
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* it sits in the VDD2_COMP rail that DSR collapses. Enable the always-on IRTC
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* wake timer as the companion counter so the OS Timer can program a wakeup and
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* resume in place. rtc0 must be okay for its wake-timer child to be usable.
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*/
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/ {
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chosen {
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zephyr,system-timer-companion = &irtc_wake;
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};
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};
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&rtc0 {
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status = "okay";
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};
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&irtc_wake {
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status = "okay";
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wakeup-source;
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};

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/prj.conf‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_PM=y
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CONFIG_PRINTK=y
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# The deep-sleep-retention (STANDBY) entry/exit path runs on the idle thread
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# stack and uses more stack than a plain WFI idle (context save/restore, clock
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# reconfiguration). Enlarge the idle stack so it does not overflow.
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CONFIG_IDLE_STACK_SIZE=2048
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# Interactive menu over the console: read the user's case selection
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# character by character.
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CONFIG_CONSOLE_SUBSYS=y
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CONFIG_CONSOLE_GETCHAR=y

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/remote/CMakeLists.txt‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(rt700_dual_core_pm_remote)
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if(NOT CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)
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message(FATAL_ERROR "${BOARD}/${BOARD_QUALIFIERS} is not supported by this sample")
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endif()
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target_sources(app PRIVATE src/main.c)
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target_include_directories(app PRIVATE
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${ZEPHYR_BASE}/../modules/hal/nxp/mcux/mcux-sdk-ng/drivers/mu1)

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/remote/Kconfig‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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source "Kconfig.zephyr"
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config RT700_DUAL_CORE_PM_SLEEP_SECONDS
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int "Power-mode measurement window in seconds"
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default 10
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range 1 3600
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help
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Number of seconds each active, sleep, or deep-sleep test case runs.

‎samples/boards/nxp/mimxrt700_evk/dual_core_pm/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf‎

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# Copyright 2026 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SECOND_CORE_MCUX=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_BUILD_OUTPUT_INFO_HEADER=y
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CONFIG_GLIKEY_MCUX_GLIKEY=y

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