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Project provides a reference basic template that can be used to build 512KB firmware application to execute in internal RAM (Application as part of the FSBL).
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Subproject ExtMemLoader is a used to generate a binary library capable of downloading an application to external memory.
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The ExtMemLoader subproject is a flash algorithm that generates a binary library capable of programming an application into external memory.
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## Introduction
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The boot ROM code uses the 512KB area in the AXI SRAM2 to store the FSBL image, Once the clock is set, the green LED (GPIO PO.01) toggles in an infinite loop with a 0.5 second period.
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## Steps to Configure, Build, Load, and Debug using the Basic Template csolution project
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> **Note:**
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> **Installed packs and extensions:**
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> - Keil.STM32N6xx_DFP.1.0.1-dev3
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> - Keil.STM32N6570-DK_BSP.1.0.0-dev
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> - Arm CMSIS Debugger 1.3.0
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> - Arm CMSIS Solution 1.62.2
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> - Cbridge27.exe
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> - STM32CubeMX.6.16.1
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> - STM32Cube_FW_U0_V1.3.0
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> - STM32_SigningTool_CLI_V2.20.0
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> - STM32CubeProgrammer_V2.18.0
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The bootROM copy FSBL image (512KB) from external Flash (Octo SPI Flash Memory) to the internal RAM (AXI SRAM2).
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In the application, once the clock is configured, the green LED (GPIO PO.01) toggles in an infinite loop with a 0.5 second period.
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## Steps to Configure, Build, Load and Debug using the Basic Template csolution project
- Project tab: Ensure the **FSBL** and **ExtMemLoader** checkbox are selected
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-Core Generator tab: Check that **Copy only necessary library files** are selected
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-Code Generator tab: Check that **Copy only necessary library files** are selected
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### Navigate to Pinout & Configuration:
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### Navigate to Pinout & Configuration
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#### System core:
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#### System core
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- CORTEX_M55M_FSBL: Enable CPU ICache and DCache
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- CORTEX_M55M_FSBL: Enable **CPU ICache** and **CPU DCache**
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- GPIO: Select PO1 pin as **GPIO_output**:
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- Pin Context Assignement: **First State Booot Loader**
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- GPIO output level: High
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- Add user label: `LED1_green`
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- GPIO output level: Low
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- Add user label: `LD1_green`
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#### Connectivity:
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#### Connectivity
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- SDMMC2: Unselect **First Stage Boot Loader**(disable this peripheral, because have configuration issue)
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- XSPI1: Unselect **First Stage Boot Loader**(disable this peripheral, because have partly conflict with PO1 `LED1_green`)
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- XSPI2: Check that **First Stage Boot Loader** and **External Memory Loader**is selected under Runtime contexts and modify following parameter settings:
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- SDMMC2: Unselect **First Stage Boot Loader**checkbox to disable this peripheral (Because have configuration issue)
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- XSPI1: Unselect **First Stage Boot Loader**checkbox to disable this peripheral (Because have partly conflict with PO1 `LD1_green`)
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- XSPI2: Check that **First Stage Boot Loader** and **External Memory Loader**are selected under Runtime contexts and modify following parameter settings:
> **Note:** Note: The OTP configuration for flash source selection is configurable via BOOTROM_CONFIG2 - OTP_WORD11 using **STM32CubeProgrammer**. For more information, please check [UM3234](https://www.st.com/resource/en/user_manual/um3234-how-to-proceed-with-boot-rom-on-stm32n6-mcus-stmicroelectronics.pdf)
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> **Note:** The OTP configuration for flash source selection is configurable via fuses in BOOTROM_CONFIG_2[8:5], OTP_WORD11 using **STM32CubeProgrammer**. Ensure that boot configuration is set to **default** to have sNOR device (connected to XSPIM_P2) attached boot. For more information, please check [UM3234](https://www.st.com/resource/en/user_manual/um3234-how-to-proceed-with-boot-rom-on-stm32n6-mcus-stmicroelectronics.pdf)
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---
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### STM32CubeMX/STM32N657X0HxQ/FSBL.cgen.yml
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- #### Comment following redundant files (temporarily issue with cmsis toolbox extension)
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- #### Comment following redundant files (temporarily issue with cmsis toolbox)
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