Bazelify everything up to Golden Gate

Author: abejgonzalez

sim/BUILD.bazel

@@ -1,6 +1,7 @@
 package(default_visibility = ["//visibility:public"])
 
 load("@buildifier_prebuilt//:rules.bzl", "buildifier")
+load("//build_rules:helpers.bzl", "firesim_genrule", "plugin_chisel_generator", "plugin_golden_gate")
 
 buildifier(
     name = "buildifier-fix",
@@ -142,3 +143,14 @@ scala_binary(
     ],
     plugins = ["@mvn//:edu_berkeley_cs_chisel3_plugin_2_13_10"],
 )
+
+# TODO: don't think this is right, goal is to have upper level projects
+# define their own generator that plugs in nicely into the build flow
+plugin_chisel_generator(
+    name = "invoke-chisel-generator",
+    generator = ":chisel-generator"
+)
+plugin_golden_gate(
+    name = "invoke-golden-gate",
+    generator = ":invoke-chisel-generator"
+)

sim/Makefile

@@ -35,7 +35,6 @@ TARGET_PROJECT ?= midasexamples
 # Users can override this to point at a collections of Makefrags.
 # The following makefrags must be present in the folder:
 #   config.mk: override configuration variables with project specifics
-#   build.mk: define the build rule generating the input FIRRTL and annotations
 #   driver.mk: define the configuration for the driver
 #   metasim.mk: define rules to run metasimulator binaries.
 TARGET_PROJECT_MAKEFRAG ?= $(firesim_base_dir)/src/main/makefrag/$(TARGET_PROJECT)
@@ -52,7 +51,6 @@ include make/utils.mk
 include $(TARGET_PROJECT_MAKEFRAG)/config.mk
 include make/config.mk
 
-include $(TARGET_PROJECT_MAKEFRAG)/build.mk
 include make/goldengate.mk
 include make/post-synth.mk
 
@@ -83,10 +81,12 @@ mostlyclean:
 .PHONY: clean
 clean:
 	rm -rf $(GENERATED_DIR) $(OUTPUT_DIR)
+	bazel clean --expunge
 
 .PHONY: veryclean
 veryclean:
 	rm -rf generated-src output
+	bazel clean --expunge
 
 # Remove all implicit suffix rules; This improves make performance substantially as it no longer
 # attempts to resolve implicit rules on 1000+ scala files.

sim/build_rules/BUILD.bazel

@@ -0,0 +1,61 @@
+def firesim_genrule(name, cmd, **kwargs):
+  appended_cmd = """
+name_quintuplet=$(PLATFORM)-$(TARGET_PROJECT)-$(DESIGN)-$(TARGET_CONFIG)-$(PLATFORM_CONFIG)
+long_name=$(DESIGN_PACKAGE).$(DESIGN).$(TARGET_CONFIG)
+BUILD_DIR=generated-src
+GENERATED_DIR=$${{BUILD_DIR}}/$(PLATFORM)/$${{name_quintuplet}}
+OUTPUT_DIR=output/$(PLATFORM)/$${{name_quintuplet}}
+FIRRTL_FILE=$${{GENERATED_DIR}}/$${{long_name}}.fir
+ANNO_FILE=$${{GENERATED_DIR}}/$${{long_name}}.anno.json
+simulator_verilog=$${{GENERATED_DIR}}/$(BASE_FILE_NAME).sv
+simulator_xdc=$${{GENERATED_DIR}}/$(BASE_FILE_NAME).synthesis.xdc
+{cmd}
+""".format(cmd=cmd)
+  native.genrule(
+    name=name,
+    cmd=appended_cmd,
+    **kwargs)
+
+def plugin_chisel_generator(name, generator):
+    firesim_genrule(
+        name = name,
+        outs = [
+            "chisel-generator.tar.gz",
+        ],
+        tools = [generator],
+        cmd = """
+    mkdir -p $$GENERATED_DIR
+    $(location {generator}) \
+            --target-dir $${{GENERATED_DIR}} \
+            --name $(NAME) \
+            --top-module $(TOP_MODULE) \
+            --configs $(CONFIGS)
+    tar czf $@ $${{GENERATED_DIR}}
+        """.format(generator=generator),
+        message = "Invoke the Chisel generator built-in with FireSim",
+    )
+
+def plugin_golden_gate(name, generator):
+    firesim_genrule(
+        name = name,
+        srcs = [generator],
+        outs = [
+            "golden-gate.tar.gz",
+        ],
+        tools = ["//midas/src/main/scala:golden-gate"],
+        cmd = """
+    tar xzf $(location {generator})
+    $(location //midas/src/main/scala:golden-gate) \
+        -i $${{FIRRTL_FILE}} \
+        -faf $${{ANNO_FILE}} \
+        -td $${{GENERATED_DIR}} \
+        -ggcp $(PLATFORM_CONFIG_PACKAGE) \
+        -ggcs $(PLATFORM_CONFIG) \
+        --output-filename-base $(BASE_FILE_NAME) \
+        --allow-unrecognized-annotations \
+        --no-dedup
+    grep -sh ^ $${{GENERATED_DIR}}/firrtl_black_box_resource_files.f | xargs cat >> $${{simulator_verilog}}
+    tar czf $@ $${{GENERATED_DIR}}
+        """.format(generator=generator),
+        message = "Invoke the GoldenGate compiler with the Chisel generator built-in with FireSim",
+    )

sim/build_rules/helpers.bzl

@@ -22,18 +22,21 @@ compile: $(simulator_verilog)
 # Disable FIRRTL 1.4 deduplication because it creates multiple failures
 # Run the 1.3 version instead (checked-in). If dedup must be completely disabled,
 # pass --no-legacy-dedup as well
-$(simulator_verilog) $(simulator_xdc) $(header) $(fame_annos) &: $(FIRRTL_FILE) $(ANNO_FILE) $(firesim_main_srcs) $(firesim_test_srcs)
-	bazel run //midas/src/main/scala:golden-gate -- \
-		-i $(FIRRTL_FILE) \
-		-td $(GENERATED_DIR) \
-		-faf $(ANNO_FILE) \
-		-ggcp $(PLATFORM_CONFIG_PACKAGE) \
-		-ggcs $(PLATFORM_CONFIG) \
-		--output-filename-base $(BASE_FILE_NAME) \
-		--allow-unrecognized-annotations \
-		--no-dedup
-	grep -sh ^ $(GENERATED_DIR)/firrtl_black_box_resource_files.f | \
-		xargs cat >> $(simulator_verilog) # Append blackboxes to FPGA wrapper, if any
+$(simulator_verilog) $(simulator_xdc) $(header) $(fame_annos) &: $(firesim_main_srcs) $(firesim_test_srcs)
+	bazel build //:invoke-golden-gate \
+		--define PLATFORM=$(PLATFORM) \
+		--define PLATFORM_CONFIG_PACKAGE=$(PLATFORM_CONFIG_PACKAGE) \
+		--define PLATFORM_CONFIG=$(PLATFORM_CONFIG) \
+		--define TARGET_PROJECT=$(TARGET_PROJECT) \
+		--define TARGET_CONFIG_PACKAGE=$(TARGET_CONFIG_PACKAGE) \
+		--define TARGET_CONFIG=$(TARGET_CONFIG) \
+		--define DESIGN_PACKAGE=$(DESIGN_PACKAGE) \
+		--define DESIGN=$(DESIGN) \
+		--define BASE_FILE_NAME=$(BASE_FILE_NAME) \
+		--define NAME=$(long_name) \
+		--define TOP_MODULE=$(DESIGN_PACKAGE).$(DESIGN) \
+		--define CONFIGS=$(TARGET_CONFIG_QUALIFIED)
+	tar xvf $(shell bazel info bazel-genfiles)/golden-gate.tar.gz
 
 ####################################
 # Runtime-Configuration Generation #