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abejgonzalezabejgonzalez
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Added Verilator testing
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‎sim/MODULE.bazel‎

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@@ -46,3 +46,23 @@ maven.install(
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],
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)
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use_repo(maven, "mvn")
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bazel_dep(name = "rules_verilator", version = "5.034")
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single_version_override(
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module_name = "rules_verilator",
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registry = "https://raw.githubusercontent.com/Pinata-Consulting/ascenium-registry/683f93e670a04f8d3d47316c42d197d8ac095a00/",
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version = "5.034",
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)
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single_version_override(
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module_name = "verilator",
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registry = "https://raw.githubusercontent.com/Pinata-Consulting/ascenium-registry/683f93e670a04f8d3d47316c42d197d8ac095a00/",
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version = "5.034.ar.1",
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)
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single_version_override(
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module_name = "systemc",
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registry = "https://raw.githubusercontent.com/Pinata-Consulting/ascenium-registry/683f93e670a04f8d3d47316c42d197d8ac095a00/",
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version = "3.0.1",
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)
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register_toolchains(
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"@rules_verilator//verilator:verilator_toolchain",
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)

‎sim/make/vcs.mk‎

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@@ -19,6 +19,14 @@ $(vcs) $(vcs_post_synth) $(vcs_debug) $(vcs_post_synth_debug): export LDFLAGS :=
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vcs_driver_deps := $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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# an example:
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# make -C .../midas/src/main/cc vcs \
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# PLATFORM=f1 \
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# DRIVER_NAME=SimpleCounterHarness \
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# GEN_FILE_BASENAME=FireSim-generated \
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# GEN_DIR=...sim/generated-src/f1/f1-examples-SimpleCounterHarness-NoConfig-F1Config \
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# DRIVER="...sim/src/main/cc/examples/simple_counter_top.cc" # could be multiple files
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# DESIGN_V=...sim/generated-src/f1/f1-examples-SimpleCounterHarness-NoConfig-F1Config/FireSim-generated.sv
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define make_vcs
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$(MAKE) -C $(simif_dir) $(1) \
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PLATFORM=$(PLATFORM) \

‎sim/midas/src/main/cc/rtlsim/BUILD.bazel‎

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load("@rules_hdl//hdl:defs.bzl", "verilator_cc_library")
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verilator_cc_library(
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name = "adder_verilator",
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module = ":adder", # should be the top level verilog file
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module_top = "emul",
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copts = [
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"-Wall",
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"-Imidas/src/main/cc",
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"-Igenerated-src/...",
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"-DVERILATOR",
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],
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vopts = [
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"--main",
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"--timing",
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"--cc",
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"--exe",
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"--timescale 1ps/1ps",
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"-O2",
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"-sv",
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"--vpi",
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"--output-split 10000",
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"--output-split-cfuncs 100",
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"-Wall",
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"-Wno-UNUSEDSIGNAL",
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"-Wno-DECLFILENAME",
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"-Wno-VARHIDDEN",
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"-Wno-UNDRIVEN",
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"TODO: LDFLAGS"
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"+define+CLOCK_PERIOD=1.0",
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"+define+RANDOMIZE_MEM_INIT",
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"+define+RANDOMIZE_REG_INIT",
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"+define+RANDOMIZE_GARBAGE_ASSIGN",
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"+define+RANDOMIZE_INVALID_ASSIGN",
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"+define+STOP_COND=!emul.reset",
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"+define+PRINTF_COND=!$emul.reset",
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"+define+RANDOM=32'b0",
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],
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)
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cc_library(
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# probably has to include the header?
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)
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# what about the driver class?

‎sim/midas/src/main/verilog/BUILD.bazel‎

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load("@rules_verilator//verilog:defs.bzl", "verilog_library")
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verilog_library(
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name = "bufgce",
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srcs = ["BUFGCE.v"],
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)
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verilog_library(
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name = "top",
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srcs = ["top.v"],
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)

‎sim/midas/src/main/verilog/testing/BUILD.bazel‎

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load("@rules_verilator//verilog:defs.bzl", "verilog_library")
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load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
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verilog_library(
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name = "counter",
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srcs = ["counter.v"],
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)
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verilator_cc_library(
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name = "counter_cc",
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module = ":counter",
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module_top = "counter",
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)
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cc_binary(
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name = "top",
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srcs = ["dut_counter.cpp"],
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deps = [":counter_cc"],
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)
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verilog_library(
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name = "counter_tb",
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srcs = ["counter_tb.v"],
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deps = [":counter"],
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)
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verilator_cc_library(
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name = "counter_tb_cc",
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module = ":counter_tb",
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module_top = "testbench",
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copts = [
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"-Wall",
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# "-DVERILATOR",
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"-fcoroutines",
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],
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vopts = [
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"--main",
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# "--exe",
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"--timing",
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"--cc",
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# "--timescale 1ps/1ps",
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"-O2",
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"-sv",
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# "--vpi",
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# "--output-split 10000",
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# "--output-split-cfuncs 100",
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"-Wall",
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"-Wno-UNUSEDSIGNAL",
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"-Wno-DECLFILENAME",
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"-Wno-VARHIDDEN",
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"-Wno-UNDRIVEN",
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# "+define+CLOCK_PERIOD=1.0",
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# "+define+RANDOMIZE_MEM_INIT",
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# "+define+RANDOMIZE_REG_INIT",
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# "+define+RANDOMIZE_GARBAGE_ASSIGN",
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# "+define+RANDOMIZE_INVALID_ASSIGN",
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# "+define+STOP_COND=!emul.reset",
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# "+define+PRINTF_COND=!emul.reset",
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# "+define+RANDOM=32\\'b0",
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],
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)
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cc_binary(
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name = "counter_tb_top",
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deps = [":counter_tb_cc"],
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copts = [
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"-fcoroutines",
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],
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)

‎sim/midas/src/main/verilog/testing/counter.v‎

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module counter(
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input clk,
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input reset,
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input enable,
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output [7:0] out
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);
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(* keep *) reg [7:0] tmp;
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always @(*) begin
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tmp = counter_reg + 1;
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end
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reg [7:0] counter_reg;
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always @(posedge clk) begin
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if (reset) begin
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counter_reg <= 0;
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end else if (enable) begin
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counter_reg <= tmp;
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end
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end
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assign out = counter_reg;
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endmodule

‎sim/midas/src/main/verilog/testing/counter_tb.v‎

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module testbench;
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// Inputs
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reg clk;
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reg reset;
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reg enable;
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// Outputs
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wire [7:0] out;
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// Instantiate the counter module
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counter uut (
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.clk(clk),
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.reset(reset),
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.enable(enable),
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.out(out)
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);
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// Clock generation
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// Stimulus
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initial begin
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// Initial values
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reset = 1;
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enable = 0;
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// Apply reset
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#10;
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reset = 0;
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// Enable the counter
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#10;
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enable = 1;
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// Run for a while
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#100;
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// Stop simulation
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$finish;
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end
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// Monitor output
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initial begin
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$monitor("Time = %0t, clk = %b, reset = %b, enable = %b, out = %d", $time, clk, reset, enable, out);
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end
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endmodule

‎sim/midas/src/main/verilog/testing/dut_counter.cpp‎

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#include <cstdio>
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#include <stdlib.h>
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#include "Vcounter.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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vluint64_t global_time = 0;
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VerilatedVcdC *tfp = 0;
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void do_terminate() {
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#ifdef VM_TRACE
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tfp->dump(global_time);
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tfp->close();
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#endif
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printf("simulation finished at cycle %lld\n", (long long)global_time);
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exit(0);
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}
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void advance_clock(Vcounter *uut) {
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uut->clk ^= 1;
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uut->eval();
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#ifdef VM_TRACE
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tfp->dump(global_time);
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#endif
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uut->clk ^= 1;
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global_time++;
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uut->eval();
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#ifdef VM_TRACE
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tfp->dump(global_time);
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#endif
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global_time++;
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}
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int main() {
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Vcounter top;
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#ifdef VM_TRACE
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// init trace dump
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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top.trace(tfp, 99);
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tfp->open("output.vcd");
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#endif
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top.clk = 1;
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top.enable = 0;
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top.reset = 1;
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advance_clock(&top);
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advance_clock(&top);
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advance_clock(&top);
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top.reset = 0;
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advance_clock(&top);
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int counter = 0;
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while (global_time < 100000) {
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bool enable = (rand() & 0xF) == 0;
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top.enable = enable;
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if (enable)
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++counter;
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advance_clock(&top);
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if (top.out != counter) {
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fprintf(stderr, "ERROR: unexpected output of %d vs %d\n", top.out, counter);
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//do_terminate();
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}
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}
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do_terminate();
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return 0;
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}

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