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Johan Peltenburg
authored
Merge pull request #263 from abs-tudelft/write-response-channel
Add write response channel & synchronization support
2 parents c878fcc + 82daca5 commit 4a93cf6

39 files changed

+1373
-412
lines changed

‎codegen/cpp/fletchgen/src/fletchgen/bus.cc‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ using cerata::parameter;
3737
using cerata::stream;
3838
using cerata::field;
3939
using cerata::vector;
40+
using cerata::bit;
4041

4142
PARAM_FACTORY(bus_addr_width)
4243
PARAM_FACTORY(bus_data_width)
@@ -61,17 +62,21 @@ std::shared_ptr<Type> bus_write(const std::shared_ptr<Node> &addr_width,
6162
const std::shared_ptr<Node> &data_width,
6263
const std::shared_ptr<Node> &len_width) {
6364
auto wreq = stream(record("", {field("addr", vector(addr_width)),
64-
field("len", vector(len_width))}));
65+
field("len", vector(len_width)),
66+
field("last", last())}));
6567
auto wdat = stream(record("", {field("data", vector(data_width)),
6668
field("strobe", vector(data_width / 8)),
6769
field("last", last())}));
70+
auto wrep = stream(record("", {field("ok", bit())}));
6871
auto result = record("", {field("wreq", wreq),
69-
field("wdat", wdat)});
72+
field("wdat", wdat),
73+
field("wrep", wrep)->Reverse()});
7074
return result;
7175
}
7276

7377
static std::string GetBusArbiterName(BusFunction function) {
74-
return std::string("Bus") + (function == BusFunction::READ ? "Read" : "Write") + "ArbiterVec";
78+
return std::string("Bus") + (function == BusFunction::READ ? "Read" : "Write")
79+
+ "ArbiterVec";
7580
}
7681

7782
Component *bus_arbiter(BusFunction function) {

‎codegen/cpp/fletchgen/src/fletchgen/top/axi.cc‎

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -125,22 +125,32 @@ std::string GenerateAXITop(const Mantle &mantle,
125125
" wr_mst_wreq_ready : in std_logic;\n"
126126
" wr_mst_wreq_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
127127
" wr_mst_wreq_len : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
128+
" wr_mst_wreq_last : out std_logic;\n"
128129
" wr_mst_wdat_valid : out std_logic;\n"
129130
" wr_mst_wdat_ready : in std_logic;\n"
130131
" wr_mst_wdat_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
131132
" wr_mst_wdat_strobe : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
132-
" wr_mst_wdat_last : out std_logic;");
133+
" wr_mst_wdat_last : out std_logic;"
134+
" wr_mst_wrep_valid : in std_logic;"
135+
" wr_mst_wrep_ready : out std_logic;"
136+
" wr_mst_wrep_ok : in std_logic;"
137+
);
133138

134139
t.Replace("MST_WREQ_INSTANTIATE",
135140
" wr_mst_wreq_valid => wr_mst_wreq_valid,\n"
136141
" wr_mst_wreq_ready => wr_mst_wreq_ready,\n"
137142
" wr_mst_wreq_addr => wr_mst_wreq_addr,\n"
138143
" wr_mst_wreq_len => wr_mst_wreq_len,\n"
144+
" wr_mst_wreq_last => wr_mst_wreq_last,\n"
139145
" wr_mst_wdat_valid => wr_mst_wdat_valid,\n"
140146
" wr_mst_wdat_ready => wr_mst_wdat_ready,\n"
141147
" wr_mst_wdat_data => wr_mst_wdat_data,\n"
142148
" wr_mst_wdat_strobe => wr_mst_wdat_strobe,\n"
143-
" wr_mst_wdat_last => wr_mst_wdat_last,");
149+
" wr_mst_wdat_last => wr_mst_wdat_last,\n"
150+
" wr_mst_wrep_valid => wr_mst_wrep_valid,\n"
151+
" wr_mst_wrep_ready => wr_mst_wrep_ready,\n"
152+
" wr_mst_wrep_ok => wr_mst_wrep_ok,");
153+
144154
t.Replace("AXI_WRITE_CONVERTER",
145155
" -----------------------------------------------------------------------------\n"
146156
" -- AXI write converter\n"
@@ -168,21 +178,29 @@ std::string GenerateAXITop(const Mantle &mantle,
168178
" slv_bus_wreq_len => wr_mst_wreq_len,\n"
169179
" slv_bus_wreq_valid => wr_mst_wreq_valid,\n"
170180
" slv_bus_wreq_ready => wr_mst_wreq_ready,\n"
181+
" slv_bus_wreq_last => wr_mst_wreq_last,\n"
171182
" slv_bus_wdat_data => wr_mst_wdat_data,\n"
172183
" slv_bus_wdat_strobe => wr_mst_wdat_strobe,\n"
173184
" slv_bus_wdat_last => wr_mst_wdat_last,\n"
174185
" slv_bus_wdat_valid => wr_mst_wdat_valid,\n"
175186
" slv_bus_wdat_ready => wr_mst_wdat_ready,\n"
187+
" slv_bus_wrep_valid => wr_mst_wrep_valid,\n"
188+
" slv_bus_wrep_ready => wr_mst_wrep_ready,\n"
189+
" slv_bus_wrep_ok => wr_mst_wrep_ok,\n"
176190
" m_axi_awaddr => m_axi_awaddr,\n"
177191
" m_axi_awlen => m_axi_awlen,\n"
178192
" m_axi_awvalid => m_axi_awvalid,\n"
179193
" m_axi_awready => m_axi_awready,\n"
180194
" m_axi_awsize => m_axi_awsize,\n"
195+
" m_axi_awuser => m_axi_awuser,\n"
181196
" m_axi_wdata => m_axi_wdata,\n"
182197
" m_axi_wstrb => m_axi_wstrb,\n"
183198
" m_axi_wlast => m_axi_wlast,\n"
184199
" m_axi_wvalid => m_axi_wvalid,\n"
185-
" m_axi_wready => m_axi_wready\n"
200+
" m_axi_wready => m_axi_wready,\n"
201+
" m_axi_bvalid => m_axi_bvalid,\n"
202+
" m_axi_bready => m_axi_bready,\n"
203+
" m_axi_bresp => m_axi_bresp\n"
186204
" );");
187205
} else {
188206
t.Replace("MST_WREQ_DECLARE", "");

‎codegen/cpp/fletchgen/src/fletchgen/top/axi_template.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,7 @@ static char axi_source[] =
100100
" m_axi_awaddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
101101
" m_axi_awlen : out std_logic_vector(7 downto 0);\n"
102102
" m_axi_awsize : out std_logic_vector(2 downto 0);\n"
103+
" m_axi_awuser : out std_logic_vector(0 downto 0);\n"
103104
"\n"
104105
" -- Write data channel\n"
105106
" m_axi_wvalid : out std_logic := '0';\n"
@@ -108,6 +109,10 @@ static char axi_source[] =
108109
" m_axi_wlast : out std_logic;\n"
109110
" m_axi_wstrb : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
110111
"\n"
112+
" -- Write response channel\n"
113+
" m_axi_bvalid : in std_logic;\n"
114+
" m_axi_bready : out std_logic;\n"
115+
" m_axi_bresp : in std_logic_vector(1 downto 0);\n"
111116
" ---------------------------------------------------------------------------\n"
112117
" -- AXI4-lite Slave as MMIO interface\n"
113118
" ---------------------------------------------------------------------------\n"
@@ -165,11 +170,16 @@ static char axi_source[] =
165170
" signal wr_mst_wreq_ready : std_logic;\n"
166171
" signal wr_mst_wreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
167172
" signal wr_mst_wreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
173+
" signal wr_mst_wreq_last : std_logic;\n"
168174
" signal wr_mst_wdat_valid : std_logic;\n"
169175
" signal wr_mst_wdat_ready : std_logic;\n"
170176
" signal wr_mst_wdat_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
171177
" signal wr_mst_wdat_strobe : std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
172178
" signal wr_mst_wdat_last : std_logic;\n"
179+
" signal wr_mst_wrep_valid : std_logic;\n"
180+
" signal wr_mst_wrep_ready : std_logic;\n"
181+
" signal wr_mst_wrep_ok : std_logic;\n"
182+
"\n"
173183
"begin\n"
174184
"\n"
175185
" -- Active low reset\n"

‎codegen/cpp/fletchgen/src/fletchgen/top/sim.cc‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -266,34 +266,46 @@ std::string GenerateSimTop(const Design &design,
266266
" wreq_ready => bus_wreq_ready,\n"
267267
" wreq_addr => bus_wreq_addr,\n"
268268
" wreq_len => bus_wreq_len,\n"
269+
" wreq_last => bus_wreq_last,\n"
269270
" wdat_valid => bus_wdat_valid,\n"
270271
" wdat_ready => bus_wdat_ready,\n"
271272
" wdat_data => bus_wdat_data,\n"
272273
" wdat_strobe => bus_wdat_strobe,\n"
273-
" wdat_last => bus_wdat_last\n"
274+
" wdat_last => bus_wdat_last,\n"
275+
" wrep_valid => bus_wrep_valid,\n"
276+
" wrep_ready => bus_wrep_ready,\n"
277+
" wrep_ok => bus_wrep_ok\n"
274278
" );");
275279

276280
t.Replace("MST_WREQ_DECLARE",
277281
" wr_mst_wreq_valid : out std_logic;\n"
278282
" wr_mst_wreq_ready : in std_logic;\n"
279283
" wr_mst_wreq_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
280284
" wr_mst_wreq_len : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
285+
" wr_mst_wreq_last : out std_logic;\n"
281286
" wr_mst_wdat_valid : out std_logic;\n"
282287
" wr_mst_wdat_ready : in std_logic;\n"
283288
" wr_mst_wdat_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
284289
" wr_mst_wdat_strobe : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
285-
" wr_mst_wdat_last : out std_logic;");
290+
" wr_mst_wdat_last : out std_logic;"
291+
" wr_mst_wrep_valid : in std_logic;\n"
292+
" wr_mst_wrep_ready : out std_logic;\n"
293+
" wr_mst_wrep_ok : in std_logic;\n");
286294

287295
t.Replace("MST_WREQ_INSTANTIATE",
288296
" wr_mst_wreq_valid => bus_wreq_valid,\n"
289297
" wr_mst_wreq_ready => bus_wreq_ready,\n"
290298
" wr_mst_wreq_addr => bus_wreq_addr,\n"
291299
" wr_mst_wreq_len => bus_wreq_len,\n"
300+
" wr_mst_wreq_last => bus_wreq_last,\n"
292301
" wr_mst_wdat_valid => bus_wdat_valid,\n"
293302
" wr_mst_wdat_ready => bus_wdat_ready,\n"
294303
" wr_mst_wdat_data => bus_wdat_data,\n"
295304
" wr_mst_wdat_strobe => bus_wdat_strobe,\n"
296-
" wr_mst_wdat_last => bus_wdat_last,");
305+
" wr_mst_wdat_last => bus_wdat_last,\n"
306+
" wr_mst_wrep_valid => bus_wrep_valid,\n"
307+
" wr_mst_wrep_ready => bus_wrep_ready,\n"
308+
" wr_mst_wrep_ok => bus_wrep_ok,");
297309
} else {
298310
t.Replace("BUS_WRITE_SLAVE_MOCK", "");
299311
t.Replace("MST_WREQ_DECLARE", "");

‎codegen/cpp/fletchgen/src/fletchgen/top/sim_template.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ static char sim_source[] =
157157
" signal bus_rdat_valid : std_logic;\n"
158158
" signal bus_rdat_ready : std_logic;\n"
159159
" signal bus_wreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
160+
" signal bus_wreq_last : std_logic;\n"
160161
" signal bus_wreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
161162
" signal bus_wreq_valid : std_logic;\n"
162163
" signal bus_wreq_ready : std_logic;\n"
@@ -165,6 +166,9 @@ static char sim_source[] =
165166
" signal bus_wdat_last : std_logic;\n"
166167
" signal bus_wdat_valid : std_logic;\n"
167168
" signal bus_wdat_ready : std_logic;\n"
169+
" signal bus_wrep_ok : std_logic;\n"
170+
" signal bus_wrep_valid : std_logic;\n"
171+
" signal bus_wrep_ready : std_logic;\n"
168172
"\n"
169173
" procedure mmio_write32 (constant idx : in natural;\n"
170174
" constant data : in std_logic_vector(31 downto 0);\n"

‎codegen/test/primmap/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
.PHONY: clean sim
22

33
all:
4-
fletchgen -r twoprimread.rb -i twoprimwrite.as -s memory.srec -l dot vhdl --sim --regs c:8:add:0x01 s:32:sum
4+
python3 generate-input.py
5+
fletchgen -r in.rb -i out.as -s memory.srec -l vhdl dot --sim --regs c:8:add:0x01 s:32:sum
56

67
sim:
78
rm -f vhdl/Kernel.gen.vhd

‎codegen/test/primmap/generate-input.py‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
import pyarrow as pa
2+
3+
# Create a field that can be interpreted as a "listprim" ArrayReader/Writer
4+
input_schema = pa.schema([pa.field('A', pa.int8(), nullable=False),
5+
pa.field('B', pa.int8(), nullable=False)])
6+
input_schema = input_schema.with_metadata({b'fletcher_mode': b'read', b'fletcher_name': b'R'})
7+
8+
output_schema = pa.schema([pa.field('C', pa.int8(), nullable=False),
9+
pa.field('D', pa.int8(), nullable=False)])
10+
output_schema = output_schema.with_metadata({b'fletcher_mode': b'write', b'fletcher_name': b'W'})
11+
12+
batch_data = [pa.array([1, -3, 3, -7], pa.int8()),
13+
pa.array([4, 2, -6, -9], pa.int8())]
14+
15+
input_batch = pa.RecordBatch.from_arrays(batch_data, schema=input_schema)
16+
writer_in = pa.RecordBatchFileWriter('in.rb', input_schema)
17+
writer_in.write(input_batch)
18+
writer_in.close()
19+
20+
serialized_out_schema = output_schema.serialize()
21+
pa.output_stream('out.as').write(serialized_out_schema)

‎codegen/test/primmap/in.rb‎

850 Bytes
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‎codegen/test/primmap/out.as‎

288 Bytes
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‎codegen/test/primmap/twoprimread.rb‎

-1.06 KB
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