@@ -556,37 +556,35 @@ bool SERCOM::startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag
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// Address Transmitted
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if ( flag == WIRE_WRITE_FLAG ) // Write mode
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{
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- while ( !sercom->I2CM .INTFLAG .bit .MB )
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- {
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+ while ( !sercom->I2CM .INTFLAG .bit .MB ) {
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// Wait transmission complete
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- // If certain errors occur, the MB bit may never be set (RFTM: SAMD21 sec:28.10.6; SAMD51 sec:36.10.7).
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- // The data transfer errors that can occur (including BUSERR) are all
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- // rolled up into INTFLAG.bit.ERROR from STATUS.reg
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- if (sercom->I2CM .INTFLAG .bit .ERROR ) {
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- return false ;
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- }
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+ // If certain errors occur, the MB bit may never be set (RFTM: SAMD21 sec:28.10.6; SAMD51 sec:36.10.7).
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+ // The data transfer errors that can occur (including BUSERR) are all
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+ // rolled up into INTFLAG.bit.ERROR from STATUS.reg
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+ if (sercom->I2CM .INTFLAG .bit .ERROR ) {
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+ return false ;
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+ }
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}
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}
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else // Read mode
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{
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- while ( !sercom->I2CM .INTFLAG .bit .SB )
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- {
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- // If the slave NACKS the address, the MB bit will be set.
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- // A variety of errors in the STATUS register can set the ERROR bit in the INTFLAG register
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- // In that case, send a stop condition and return false.
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- if (sercom->I2CM .INTFLAG .bit .ERROR || sercom->I2CM .INTFLAG .bit .MB ) {
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- sercom->I2CM .CTRLB .bit .CMD = 3 ; // Stop condition
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- return false ;
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- }
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+ while ( !sercom->I2CM .INTFLAG .bit .SB ) {
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// Wait transmission complete
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+
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+ // If the slave NACKS the address, the MB bit will be set.
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+ // A variety of errors in the STATUS register can set the ERROR bit in the INTFLAG register
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+ // In that case, send a stop condition and return false.
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+ if (sercom->I2CM .INTFLAG .bit .MB || sercom->I2CM .INTFLAG .bit .ERROR ) {
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+ sercom->I2CM .CTRLB .bit .CMD = 3 ; // Stop condition
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+ return false ;
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+ }
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}
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// Clean the 'Slave on Bus' flag, for further usage.
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// sercom->I2CM.INTFLAG.bit.SB = 0x1ul;
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}
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-
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// ACK received (0: ACK, 1: NACK)
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if (sercom->I2CM .STATUS .bit .RXNACK )
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{
@@ -605,11 +603,10 @@ bool SERCOM::sendDataMasterWIRE(uint8_t data)
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// Wait transmission successful
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while (!sercom->I2CM .INTFLAG .bit .MB ) {
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-
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// If a data transfer error occurs, the MB bit may never be set.
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// Check the error bit and bail if it's set.
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// The data transfer errors that can occur (including BUSERR) are all
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- // rolled up into INTFLAG.bit.ERROR from STATUS.reg
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+ // rolled up into INTFLAG.bit.ERROR from STATUS.reg
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if (sercom->I2CM .INTFLAG .bit .ERROR ) {
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return false ;
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}
@@ -711,18 +708,17 @@ uint8_t SERCOM::readDataWIRE( void )
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{
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if (isMasterWIRE ())
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{
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- while ( sercom->I2CM .INTFLAG .bit .SB == 0 )
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- {
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+ while (sercom->I2CM .INTFLAG .bit .SB == 0 ) {
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// Waiting complete receive
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- // A variety of errors in the STATUS register can set the ERROR bit in the INTFLAG register
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+ // A variety of errors in the STATUS register can set the ERROR bit in the INTFLAG register
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// In that case, send a stop condition and return false.
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- // readDataWIRE should really be able to indicate an error (which would never be used
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- // because the readDataWIRE callers (in Wire.cpp) should have checked availableWIRE() first and timed it
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- // out if the data never showed up
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- if (sercom->I2CM .INTFLAG .bit .ERROR || sercom->I2CM .INTFLAG .bit .MB ) {
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- sercom->I2CM .CTRLB .bit .CMD = 3 ; // Stop condition
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- return 0xFF ;
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- }
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+ // readDataWIRE should really be able to indicate an error (which would never be used
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+ // because the readDataWIRE callers (in Wire.cpp) should have checked availableWIRE() first and timed it
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+ // out if the data never showed up
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+ if (sercom->I2CM .INTFLAG .bit .MB || sercom->I2CM .INTFLAG .bit .ERROR ) {
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+ sercom->I2CM .CTRLB .bit .CMD = 3 ; // Stop condition
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+ return 0xFF ;
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+ }
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}
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return sercom->I2CM .DATA .bit .DATA ;
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