Merge pull request #51 from alainmarcel/fix_tests

fix tests: enum

Author: alaindargelas

CMakeLists.txt

@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
 
-project(uhdm2rtlil VERSION 1.0)
+project(uhdm2rtlil VERSION 1.86)
 
 # Set C++ standard
 set(CMAKE_CXX_STANDARD 17)

src/frontends/uhdm/expression.cpp

@@ -860,9 +860,39 @@ RTLIL::SigSpec UhdmImporter::import_ref_obj(const ref_obj* uhdm_ref, const UHDM:
         return RTLIL::SigSpec(RTLIL::Const(value, 32));
     }
 
-    // Check if the ref_obj has an Actual_group() that points to a parameter
+    // Check if the ref_obj has an Actual_group() that points to a parameter or enum constant
     if (uhdm_ref->Actual_group()) {
         const any* actual = uhdm_ref->Actual_group();
+        
+        // Check for enum constant
+        if (actual->UhdmType() == uhdmenum_const) {
+            const UHDM::enum_const* enum_val = any_cast<const UHDM::enum_const*>(actual);
+            // Get the enum value - enum constants store their value in VpiValue
+            std::string val_str = std::string(enum_val->VpiValue());
+            
+            if (mode_debug)
+                log("UHDM: Found enum constant %s with value %s\n", ref_name.c_str(), val_str.c_str());
+            
+            // Parse value from format like "INT:0", "UINT:1", etc.
+            RTLIL::Const enum_value;
+            if (!val_str.empty()) {
+                size_t colon_pos = val_str.find(':');
+                if (colon_pos != std::string::npos) {
+                    std::string value_part = val_str.substr(colon_pos + 1);
+                    // Parse as integer
+                    enum_value = RTLIL::Const(std::stoi(value_part), 32);
+                } else {
+                    // Try to parse as integer directly
+                    enum_value = RTLIL::Const(std::stoi(val_str), 32);
+                }
+            } else {
+                // Default to 0 if no value specified
+                enum_value = RTLIL::Const(0, 32);
+            }
+            
+            return RTLIL::SigSpec(enum_value);
+        }
+        
         if (actual->VpiType() == vpiParameter) {
             const parameter* param = any_cast<const parameter*>(actual);
             // Get the parameter value - parameters typically store values as constants

src/frontends/uhdm/module.cpp

@@ -1341,6 +1341,22 @@ int UhdmImporter::get_width_from_typespec(const UHDM::any* typespec, const UHDM:
             return -1;  // Special value to indicate interface type
         }
 
+        // Check if this is an enum typespec - need to get the base type
+        if (typespec->UhdmType() == uhdmenum_typespec) {
+            log("UHDM: Found enum_typespec, getting base type\n");
+            if (auto enum_typespec = dynamic_cast<const UHDM::enum_typespec*>(typespec)) {
+                // Get the base typespec - this defines the actual width
+                if (auto base_typespec = enum_typespec->Base_typespec()) {
+                    log("UHDM: Found base typespec for enum\n");
+                    return get_width_from_typespec(base_typespec, inst);
+                } else {
+                    // No explicit base type means default int type (32 bits in SystemVerilog)
+                    log("UHDM: No base typespec for enum, defaulting to 32 bits\n");
+                    return 32;
+                }
+            }
+        }
+        
         // Use UHDM::ExprEval to get the actual size of the typespec
         UHDM::ExprEval eval;
         bool invalidValue = false;

src/frontends/uhdm/process.cpp

@@ -4573,6 +4573,7 @@ void UhdmImporter::import_case_stmt_sync(const case_stmt* uhdm_case, RTLIL::Sync
         // First, collect all assignments from all case items
         std::map<std::string, std::vector<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>>> signal_assignments;
         std::vector<RTLIL::SigSpec> case_conditions;
+        RTLIL::SigSpec all_non_default_conditions;  // Track all non-default conditions
 
         // Process each case item
         if (auto case_items = uhdm_case->Case_items()) {
@@ -4582,6 +4583,7 @@ void UhdmImporter::import_case_stmt_sync(const case_stmt* uhdm_case, RTLIL::Sync
             for (auto case_item : *case_items) {
                 // Get case expressions (values to match)
                 RTLIL::SigSpec case_condition;
+                bool is_default = false;
 
                 if (auto exprs = case_item->VpiExprs()) {
                     // Build equality comparison for this case
@@ -4603,8 +4605,19 @@ void UhdmImporter::import_case_stmt_sync(const case_stmt* uhdm_case, RTLIL::Sync
                             log_flush();
                         }
                     }
+                    
+                    // Add this condition to the combined non-default conditions
+                    if (!case_condition.empty()) {
+                        if (all_non_default_conditions.empty()) {
+                            all_non_default_conditions = case_condition;
+                        } else {
+                            // OR with other non-default conditions
+                            all_non_default_conditions = create_or_cell(all_non_default_conditions, case_condition);
+                        }
+                    }
                 } else {
                     // This is a default case
+                    is_default = true;
                     log("          Default case\n");
                     log_flush();
                 }
@@ -4618,7 +4631,23 @@ void UhdmImporter::import_case_stmt_sync(const case_stmt* uhdm_case, RTLIL::Sync
                     RTLIL::SigSpec prev_condition = current_condition;
 
                     // Set condition for nested statements
-                    if (!case_condition.empty()) {
+                    if (is_default) {
+                        // For default case, use the negation of all other conditions
+                        if (!all_non_default_conditions.empty()) {
+                            // Create NOT of all non-default conditions
+                            RTLIL::Wire* not_wire = module->addWire(NEW_ID, 1);
+                            module->addNotGate(NEW_ID, all_non_default_conditions, not_wire);
+                            RTLIL::SigSpec default_condition(not_wire);
+                            
+                            if (current_condition.empty()) {
+                                current_condition = default_condition;
+                            } else {
+                                // AND with existing condition
+                                current_condition = create_and_cell(current_condition, default_condition);
+                            }
+                            log("          Using negation of all non-default conditions for default case\n");
+                        }
+                    } else if (!case_condition.empty()) {
                         if (current_condition.empty()) {
                             current_condition = case_condition;
                         } else {