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uart_tx.syr
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Release 12.1 - xst M.53d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Reading design: uart_tx.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "uart_tx.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "uart_tx"
Output Format : NGC
Target Device : xc6slx16-3-csg324
---- Source Options
Top Module Name : uart_tx
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : auto
Reduce Control Sets : auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Library Search Order : uart_tx.lso
Keep Hierarchy : NO
Netlist Hierarchy : as_optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing Verilog file "\\ad\eng\users\a\l\alexw\Desktop\Router\uart_tx.v" into library work
Parsing module <uart_tx>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <uart_tx>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <uart_tx>.
Related source file is "//ad/eng/users/a/l/alexw/desktop/router/uart_tx.v".
Found 1-bit register for signal <uart_out>.
Found 3-bit register for signal <byte_state>.
Found 4-bit register for signal <uart_state>.
Found 1-bit register for signal <data_sent>.
Found 4-bit adder for signal <uart_state[3]_GND_1_o_add_19_OUT> created at line 169.
Found 3-bit adder for signal <byte_state[2]_GND_1_o_add_21_OUT> created at line 177.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 9 D-type flip-flop(s).
inferred 51 Multiplexer(s).
Unit <uart_tx> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
3-bit adder : 1
4-bit adder : 1
# Registers : 4
1-bit register : 2
3-bit register : 1
4-bit register : 1
# Multiplexers : 51
1-bit 2-to-1 multiplexer : 42
3-bit 2-to-1 multiplexer : 1
4-bit 2-to-1 multiplexer : 8
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <uart_tx>.
The following registers are absorbed into counter <byte_state>: 1 register on signal <byte_state>.
Unit <uart_tx> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
4-bit adder : 1
# Counters : 1
3-bit up counter : 1
# Registers : 6
Flip-Flops : 6
# Multiplexers : 50
1-bit 2-to-1 multiplexer : 42
4-bit 2-to-1 multiplexer : 8
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <uart_tx> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart_tx, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 9
Flip-Flops : 9
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : uart_tx.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 27
# LUT2 : 2
# LUT3 : 2
# LUT4 : 2
# LUT5 : 4
# LUT6 : 17
# FlipFlops/Latches : 9
# FDC : 4
# FDCE : 3
# FDE : 1
# FDPE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 43
# IBUF : 42
# OBUF : 1
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-3
Slice Logic Utilization:
Number of Slice Registers: 9 out of 18224 0%
Number of Slice LUTs: 27 out of 9112 0%
Number used as Logic: 27 out of 9112 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 28
Number with an unused Flip Flop: 19 out of 28 67%
Number with an unused LUT: 1 out of 28 3%
Number of fully used LUT-FF pairs: 8 out of 28 28%
Number of unique control sets: 4
IO Utilization:
Number of IOs: 44
Number of bonded IOBs: 44 out of 232 18%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk_19k2 | BUFGP | 9 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 4.575ns (Maximum Frequency: 218.563MHz)
Minimum input arrival time before clock: 5.300ns
Maximum output required time after clock: 3.819ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk_19k2'
Clock period: 4.575ns (frequency: 218.563MHz)
Total number of paths / destination ports: 100 / 13
-------------------------------------------------------------------------
Delay: 4.575ns (Levels of Logic = 4)
Source: byte_state_1 (FF)
Destination: uart_out (FF)
Source Clock: clk_19k2 rising
Destination Clock: clk_19k2 rising
Data Path: byte_state_1 to uart_out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 12 0.525 1.017 byte_state_1 (byte_state_1)
LUT6:I4->O 1 0.250 0.688 uart_state[3]_PWR_1_o_Mux_26_o11 (uart_state[3]_PWR_1_o_Mux_26_o11)
LUT6:I4->O 1 0.250 0.580 uart_state[3]_PWR_1_o_Mux_26_o12 (uart_state[3]_PWR_1_o_Mux_26_o12)
LUT6:I5->O 1 0.254 0.688 uart_state[3]_PWR_1_o_Mux_26_o14 (uart_state[3]_PWR_1_o_Mux_26_o14)
LUT6:I4->O 1 0.250 0.000 uart_state[3]_PWR_1_o_Mux_26_o15 (uart_state[3]_PWR_1_o_Mux_26_o)
FDPE:D 0.074 uart_out
----------------------------------------
Total 4.575ns (1.603ns logic, 2.972ns route)
(35.0% logic, 65.0% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_19k2'
Total number of paths / destination ports: 51 / 12
-------------------------------------------------------------------------
Offset: 5.300ns (Levels of Logic = 5)
Source: byte0<5> (PAD)
Destination: uart_out (FF)
Destination Clock: clk_19k2 rising
Data Path: byte0<5> to uart_out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.228 1.035 byte0_5_IBUF (byte0_5_IBUF)
LUT6:I0->O 1 0.254 0.688 uart_state[3]_PWR_1_o_Mux_26_o11 (uart_state[3]_PWR_1_o_Mux_26_o11)
LUT6:I4->O 1 0.250 0.580 uart_state[3]_PWR_1_o_Mux_26_o12 (uart_state[3]_PWR_1_o_Mux_26_o12)
LUT6:I5->O 1 0.254 0.688 uart_state[3]_PWR_1_o_Mux_26_o14 (uart_state[3]_PWR_1_o_Mux_26_o14)
LUT6:I4->O 1 0.250 0.000 uart_state[3]_PWR_1_o_Mux_26_o15 (uart_state[3]_PWR_1_o_Mux_26_o)
FDPE:D 0.074 uart_out
----------------------------------------
Total 5.300ns (2.310ns logic, 2.990ns route)
(43.6% logic, 56.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_19k2'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.819ns (Levels of Logic = 1)
Source: uart_out (FF)
Destination: uart_out (PAD)
Source Clock: clk_19k2 rising
Data Path: uart_out to uart_out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 1 0.525 0.579 uart_out (uart_out_OBUF)
OBUF:I->O 2.715 uart_out_OBUF (uart_out)
----------------------------------------
Total 3.819ns (3.240ns logic, 0.579ns route)
(84.8% logic, 15.2% route)
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.98 secs
-->
Total memory usage is 143280 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)