forked from jcmvbkbc/gcc-xtensa
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathira-lives.c
1625 lines (1425 loc) · 46.4 KB
/
ira-lives.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* IRA processing allocno lives to build allocno live ranges.
Copyright (C) 2006-2013 Free Software Foundation, Inc.
Contributed by Vladimir Makarov <[email protected]>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "regs.h"
#include "rtl.h"
#include "tm_p.h"
#include "target.h"
#include "flags.h"
#include "except.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "insn-config.h"
#include "recog.h"
#include "diagnostic-core.h"
#include "params.h"
#include "df.h"
#include "sbitmap.h"
#include "sparseset.h"
#include "ira-int.h"
/* The code in this file is similar to one in global but the code
works on the allocno basis and creates live ranges instead of
pseudo-register conflicts. */
/* Program points are enumerated by numbers from range
0..IRA_MAX_POINT-1. There are approximately two times more program
points than insns. Program points are places in the program where
liveness info can be changed. In most general case (there are more
complicated cases too) some program points correspond to places
where input operand dies and other ones correspond to places where
output operands are born. */
int ira_max_point;
/* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
live ranges with given start/finish point. */
live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
/* Number of the current program point. */
static int curr_point;
/* Point where register pressure excess started or -1 if there is no
register pressure excess. Excess pressure for a register class at
some point means that there are more allocnos of given register
class living at the point than number of hard-registers of the
class available for the allocation. It is defined only for
pressure classes. */
static int high_pressure_start_point[N_REG_CLASSES];
/* Objects live at current point in the scan. */
static sparseset objects_live;
/* A temporary bitmap used in functions that wish to avoid visiting an allocno
multiple times. */
static sparseset allocnos_processed;
/* Set of hard regs (except eliminable ones) currently live. */
static HARD_REG_SET hard_regs_live;
/* The loop tree node corresponding to the current basic block. */
static ira_loop_tree_node_t curr_bb_node;
/* The number of the last processed call. */
static int last_call_num;
/* The number of last call at which given allocno was saved. */
static int *allocno_saved_at_call;
/* Record the birth of hard register REGNO, updating hard_regs_live and
hard reg conflict information for living allocnos. */
static void
make_hard_regno_born (int regno)
{
unsigned int i;
SET_HARD_REG_BIT (hard_regs_live, regno);
EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
{
ira_object_t obj = ira_object_id_map[i];
SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
}
}
/* Process the death of hard register REGNO. This updates
hard_regs_live. */
static void
make_hard_regno_dead (int regno)
{
CLEAR_HARD_REG_BIT (hard_regs_live, regno);
}
/* Record the birth of object OBJ. Set a bit for it in objects_live,
start a new live range for it if necessary and update hard register
conflicts. */
static void
make_object_born (ira_object_t obj)
{
live_range_t lr = OBJECT_LIVE_RANGES (obj);
sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live);
IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live);
if (lr == NULL
|| (lr->finish != curr_point && lr->finish + 1 != curr_point))
ira_add_live_range_to_object (obj, curr_point, -1);
}
/* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
associated with object OBJ. */
static void
update_allocno_pressure_excess_length (ira_object_t obj)
{
ira_allocno_t a = OBJECT_ALLOCNO (obj);
int start, i;
enum reg_class aclass, pclass, cl;
live_range_t p;
aclass = ALLOCNO_CLASS (a);
pclass = ira_pressure_class_translate[aclass];
for (i = 0;
(cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
if (! ira_reg_pressure_class_p[cl])
continue;
if (high_pressure_start_point[cl] < 0)
continue;
p = OBJECT_LIVE_RANGES (obj);
ira_assert (p != NULL);
start = (high_pressure_start_point[cl] > p->start
? high_pressure_start_point[cl] : p->start);
ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
}
}
/* Process the death of object OBJ, which is associated with allocno
A. This finishes the current live range for it. */
static void
make_object_dead (ira_object_t obj)
{
live_range_t lr;
sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
lr = OBJECT_LIVE_RANGES (obj);
ira_assert (lr != NULL);
lr->finish = curr_point;
update_allocno_pressure_excess_length (obj);
}
/* The current register pressures for each pressure class for the current
basic block. */
static int curr_reg_pressure[N_REG_CLASSES];
/* Record that register pressure for PCLASS increased by N registers.
Update the current register pressure, maximal register pressure for
the current BB and the start point of the register pressure
excess. */
static void
inc_register_pressure (enum reg_class pclass, int n)
{
int i;
enum reg_class cl;
for (i = 0;
(cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
if (! ira_reg_pressure_class_p[cl])
continue;
curr_reg_pressure[cl] += n;
if (high_pressure_start_point[cl] < 0
&& (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
high_pressure_start_point[cl] = curr_point;
if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
}
}
/* Record that register pressure for PCLASS has decreased by NREGS
registers; update current register pressure, start point of the
register pressure excess, and register pressure excess length for
living allocnos. */
static void
dec_register_pressure (enum reg_class pclass, int nregs)
{
int i;
unsigned int j;
enum reg_class cl;
bool set_p = false;
for (i = 0;
(cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
if (! ira_reg_pressure_class_p[cl])
continue;
curr_reg_pressure[cl] -= nregs;
ira_assert (curr_reg_pressure[cl] >= 0);
if (high_pressure_start_point[cl] >= 0
&& curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
set_p = true;
}
if (set_p)
{
EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
update_allocno_pressure_excess_length (ira_object_id_map[j]);
for (i = 0;
(cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
if (! ira_reg_pressure_class_p[cl])
continue;
if (high_pressure_start_point[cl] >= 0
&& curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
high_pressure_start_point[cl] = -1;
}
}
}
/* Determine from the objects_live bitmap whether REGNO is currently live,
and occupies only one object. Return false if we have no information. */
static bool
pseudo_regno_single_word_and_live_p (int regno)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
ira_object_t obj;
if (a == NULL)
return false;
if (ALLOCNO_NUM_OBJECTS (a) > 1)
return false;
obj = ALLOCNO_OBJECT (a, 0);
return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
}
/* Mark the pseudo register REGNO as live. Update all information about
live ranges and register pressure. */
static void
mark_pseudo_regno_live (int regno)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
enum reg_class pclass;
int i, n, nregs;
if (a == NULL)
return;
/* Invalidate because it is referenced. */
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
if (n > 1)
{
/* We track every subobject separately. */
gcc_assert (nregs == n);
nregs = 1;
}
for (i = 0; i < n; i++)
{
ira_object_t obj = ALLOCNO_OBJECT (a, i);
if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
continue;
inc_register_pressure (pclass, nregs);
make_object_born (obj);
}
}
/* Like mark_pseudo_regno_live, but try to only mark one subword of
the pseudo as live. SUBWORD indicates which; a value of 0
indicates the low part. */
static void
mark_pseudo_regno_subword_live (int regno, int subword)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
int n;
enum reg_class pclass;
ira_object_t obj;
if (a == NULL)
return;
/* Invalidate because it is referenced. */
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
if (n == 1)
{
mark_pseudo_regno_live (regno);
return;
}
pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
gcc_assert
(n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
obj = ALLOCNO_OBJECT (a, subword);
if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
return;
inc_register_pressure (pclass, 1);
make_object_born (obj);
}
/* Mark the register REG as live. Store a 1 in hard_regs_live for
this register, record how many consecutive hardware registers it
actually needs. */
static void
mark_hard_reg_live (rtx reg)
{
int regno = REGNO (reg);
if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
{
int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
enum reg_class aclass, pclass;
while (regno < last)
{
if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
&& ! TEST_HARD_REG_BIT (eliminable_regset, regno))
{
aclass = ira_hard_regno_allocno_class[regno];
pclass = ira_pressure_class_translate[aclass];
inc_register_pressure (pclass, 1);
make_hard_regno_born (regno);
}
regno++;
}
}
}
/* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
register number; ORIG_REG is the access in the insn, which may be a
subreg. */
static void
mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
{
if (df_read_modify_subreg_p (orig_reg))
{
mark_pseudo_regno_subword_live (regno,
subreg_lowpart_p (orig_reg) ? 0 : 1);
}
else
mark_pseudo_regno_live (regno);
}
/* Mark the register referenced by use or def REF as live. */
static void
mark_ref_live (df_ref ref)
{
rtx reg = DF_REF_REG (ref);
rtx orig_reg = reg;
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
mark_pseudo_reg_live (orig_reg, REGNO (reg));
else
mark_hard_reg_live (reg);
}
/* Mark the pseudo register REGNO as dead. Update all information about
live ranges and register pressure. */
static void
mark_pseudo_regno_dead (int regno)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
int n, i, nregs;
enum reg_class cl;
if (a == NULL)
return;
/* Invalidate because it is referenced. */
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
if (n > 1)
{
/* We track every subobject separately. */
gcc_assert (nregs == n);
nregs = 1;
}
for (i = 0; i < n; i++)
{
ira_object_t obj = ALLOCNO_OBJECT (a, i);
if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
continue;
dec_register_pressure (cl, nregs);
make_object_dead (obj);
}
}
/* Like mark_pseudo_regno_dead, but called when we know that only part of the
register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
static void
mark_pseudo_regno_subword_dead (int regno, int subword)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
int n;
enum reg_class cl;
ira_object_t obj;
if (a == NULL)
return;
/* Invalidate because it is referenced. */
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
if (n == 1)
/* The allocno as a whole doesn't die in this case. */
return;
cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
gcc_assert
(n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
obj = ALLOCNO_OBJECT (a, subword);
if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
return;
dec_register_pressure (cl, 1);
make_object_dead (obj);
}
/* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the
register. */
static void
mark_hard_reg_dead (rtx reg)
{
int regno = REGNO (reg);
if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
{
int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
enum reg_class aclass, pclass;
while (regno < last)
{
if (TEST_HARD_REG_BIT (hard_regs_live, regno))
{
aclass = ira_hard_regno_allocno_class[regno];
pclass = ira_pressure_class_translate[aclass];
dec_register_pressure (pclass, 1);
make_hard_regno_dead (regno);
}
regno++;
}
}
}
/* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
register number; ORIG_REG is the access in the insn, which may be a
subreg. */
static void
mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
{
if (df_read_modify_subreg_p (orig_reg))
{
mark_pseudo_regno_subword_dead (regno,
subreg_lowpart_p (orig_reg) ? 0 : 1);
}
else
mark_pseudo_regno_dead (regno);
}
/* Mark the register referenced by definition DEF as dead, if the
definition is a total one. */
static void
mark_ref_dead (df_ref def)
{
rtx reg = DF_REF_REG (def);
rtx orig_reg = reg;
if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
return;
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
&& (GET_CODE (orig_reg) != SUBREG
|| REGNO (reg) < FIRST_PSEUDO_REGISTER
|| !df_read_modify_subreg_p (orig_reg)))
return;
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
mark_pseudo_reg_dead (orig_reg, REGNO (reg));
else
mark_hard_reg_dead (reg);
}
/* If REG is a pseudo or a subreg of it, and the class of its allocno
intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
rtx actually accessed, it may be identical to DREG or a subreg of it.
Advance the current program point before making the conflict if
ADVANCE_P. Return TRUE if we will need to advance the current
program point. */
static bool
make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
bool advance_p)
{
rtx orig_reg = reg;
ira_allocno_t a;
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
return advance_p;
a = ira_curr_regno_allocno_map[REGNO (reg)];
if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
return advance_p;
if (advance_p)
curr_point++;
mark_pseudo_reg_live (orig_reg, REGNO (reg));
mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
mark_pseudo_reg_dead (orig_reg, REGNO (reg));
mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
return false;
}
/* Check and make if necessary conflicts for pseudo DREG of class
DEF_CL of the current insn with input operand USE of class USE_CL.
ORIG_DREG is the rtx actually accessed, it may be identical to
DREG or a subreg of it. Advance the current program point before
making the conflict if ADVANCE_P. Return TRUE if we will need to
advance the current program point. */
static bool
check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
enum reg_class def_cl, int use,
enum reg_class use_cl, bool advance_p)
{
if (! reg_classes_intersect_p (def_cl, use_cl))
return advance_p;
advance_p = make_pseudo_conflict (recog_data.operand[use],
use_cl, dreg, orig_dreg, advance_p);
/* Reload may end up swapping commutative operands, so you
have to take both orderings into account. The
constraints for the two operands can be completely
different. (Indeed, if the constraints for the two
operands are the same for all alternatives, there's no
point marking them as commutative.) */
if (use < recog_data.n_operands - 1
&& recog_data.constraints[use][0] == '%')
advance_p
= make_pseudo_conflict (recog_data.operand[use + 1],
use_cl, dreg, orig_dreg, advance_p);
if (use >= 1
&& recog_data.constraints[use - 1][0] == '%')
advance_p
= make_pseudo_conflict (recog_data.operand[use - 1],
use_cl, dreg, orig_dreg, advance_p);
return advance_p;
}
/* Check and make if necessary conflicts for definition DEF of class
DEF_CL of the current insn with input operands. Process only
constraints of alternative ALT. */
static void
check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
{
int use, use_match;
ira_allocno_t a;
enum reg_class use_cl, acl;
bool advance_p;
rtx dreg = recog_data.operand[def];
rtx orig_dreg = dreg;
if (def_cl == NO_REGS)
return;
if (GET_CODE (dreg) == SUBREG)
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
return;
a = ira_curr_regno_allocno_map[REGNO (dreg)];
acl = ALLOCNO_CLASS (a);
if (! reg_classes_intersect_p (acl, def_cl))
return;
advance_p = true;
for (use = 0; use < recog_data.n_operands; use++)
{
int alt1;
if (use == def || recog_data.operand_type[use] == OP_OUT)
continue;
if (recog_op_alt[use][alt].anything_ok)
use_cl = ALL_REGS;
else
use_cl = recog_op_alt[use][alt].cl;
/* If there's any alternative that allows USE to match DEF, do not
record a conflict. If that causes us to create an invalid
instruction due to the earlyclobber, reload must fix it up. */
for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
if (recog_op_alt[use][alt1].matches == def
|| (use < recog_data.n_operands - 1
&& recog_data.constraints[use][0] == '%'
&& recog_op_alt[use + 1][alt1].matches == def)
|| (use >= 1
&& recog_data.constraints[use - 1][0] == '%'
&& recog_op_alt[use - 1][alt1].matches == def))
break;
if (alt1 < recog_data.n_alternatives)
continue;
advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
use, use_cl, advance_p);
if ((use_match = recog_op_alt[use][alt].matches) >= 0)
{
if (use_match == def)
continue;
if (recog_op_alt[use_match][alt].anything_ok)
use_cl = ALL_REGS;
else
use_cl = recog_op_alt[use_match][alt].cl;
advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
use, use_cl, advance_p);
}
}
}
/* Make conflicts of early clobber pseudo registers of the current
insn with its inputs. Avoid introducing unnecessary conflicts by
checking classes of the constraints and pseudos because otherwise
significant code degradation is possible for some targets. */
static void
make_early_clobber_and_input_conflicts (void)
{
int alt;
int def, def_match;
enum reg_class def_cl;
for (alt = 0; alt < recog_data.n_alternatives; alt++)
for (def = 0; def < recog_data.n_operands; def++)
{
def_cl = NO_REGS;
if (recog_op_alt[def][alt].earlyclobber)
{
if (recog_op_alt[def][alt].anything_ok)
def_cl = ALL_REGS;
else
def_cl = recog_op_alt[def][alt].cl;
check_and_make_def_conflict (alt, def, def_cl);
}
if ((def_match = recog_op_alt[def][alt].matches) >= 0
&& (recog_op_alt[def_match][alt].earlyclobber
|| recog_op_alt[def][alt].earlyclobber))
{
if (recog_op_alt[def_match][alt].anything_ok)
def_cl = ALL_REGS;
else
def_cl = recog_op_alt[def_match][alt].cl;
check_and_make_def_conflict (alt, def, def_cl);
}
}
}
/* Mark early clobber hard registers of the current INSN as live (if
LIVE_P) or dead. Return true if there are such registers. */
static bool
mark_hard_reg_early_clobbers (rtx insn, bool live_p)
{
df_ref *def_rec;
bool set_p = false;
for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
if (DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MUST_CLOBBER))
{
rtx dreg = DF_REF_REG (*def_rec);
if (GET_CODE (dreg) == SUBREG)
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
continue;
/* Hard register clobbers are believed to be early clobber
because there is no way to say that non-operand hard
register clobbers are not early ones. */
if (live_p)
mark_ref_live (*def_rec);
else
mark_ref_dead (*def_rec);
set_p = true;
}
return set_p;
}
/* Checks that CONSTRAINTS permits to use only one hard register. If
it is so, the function returns the class of the hard register.
Otherwise it returns NO_REGS. */
static enum reg_class
single_reg_class (const char *constraints, rtx op, rtx equiv_const)
{
int curr_alt, c;
bool ignore_p;
enum reg_class cl, next_cl;
cl = NO_REGS;
for (ignore_p = false, curr_alt = 0;
(c = *constraints);
constraints += CONSTRAINT_LEN (c, constraints))
if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
{
curr_alt++;
ignore_p = false;
}
else if (! ignore_p)
switch (c)
{
case ' ':
case '\t':
case '=':
case '+':
case '*':
case '&':
case '%':
case '!':
case '?':
break;
case 'i':
if (CONSTANT_P (op)
|| (equiv_const != NULL_RTX && CONSTANT_P (equiv_const)))
return NO_REGS;
break;
case 'n':
if (CONST_SCALAR_INT_P (op)
|| (equiv_const != NULL_RTX && CONST_SCALAR_INT_P (equiv_const)))
return NO_REGS;
break;
case 's':
if ((CONSTANT_P (op) && !CONST_SCALAR_INT_P (op))
|| (equiv_const != NULL_RTX
&& CONSTANT_P (equiv_const)
&& !CONST_SCALAR_INT_P (equiv_const)))
return NO_REGS;
break;
case 'I':
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P':
if ((CONST_INT_P (op)
&& CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, constraints))
|| (equiv_const != NULL_RTX
&& CONST_INT_P (equiv_const)
&& CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const),
c, constraints)))
return NO_REGS;
break;
case 'E':
case 'F':
if (CONST_DOUBLE_AS_FLOAT_P (op)
|| (GET_CODE (op) == CONST_VECTOR
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)
|| (equiv_const != NULL_RTX
&& (CONST_DOUBLE_AS_FLOAT_P (equiv_const)
|| (GET_CODE (equiv_const) == CONST_VECTOR
&& (GET_MODE_CLASS (GET_MODE (equiv_const))
== MODE_VECTOR_FLOAT)))))
return NO_REGS;
break;
case 'G':
case 'H':
if ((CONST_DOUBLE_AS_FLOAT_P (op)
&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, constraints))
|| (equiv_const != NULL_RTX
&& CONST_DOUBLE_AS_FLOAT_P (equiv_const)
&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const,
c, constraints)))
return NO_REGS;
/* ??? what about memory */
case 'r':
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
case 'h': case 'j': case 'k': case 'l':
case 'q': case 't': case 'u':
case 'v': case 'w': case 'x': case 'y': case 'z':
case 'A': case 'B': case 'C': case 'D':
case 'Q': case 'R': case 'S': case 'T': case 'U':
case 'W': case 'Y': case 'Z':
next_cl = (c == 'r'
? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c, constraints));
if (cl == NO_REGS
? ira_class_singleton[next_cl][GET_MODE (op)] < 0
: (ira_class_singleton[cl][GET_MODE (op)]
!= ira_class_singleton[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
next_cl
= single_reg_class (recog_data.constraints[c - '0'],
recog_data.operand[c - '0'], NULL_RTX);
if (cl == NO_REGS
? ira_class_singleton[next_cl][GET_MODE (op)] < 0
: (ira_class_singleton[cl][GET_MODE (op)]
!= ira_class_singleton[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
break;
default:
return NO_REGS;
}
return cl;
}
/* The function checks that operand OP_NUM of the current insn can use
only one hard register. If it is so, the function returns the
class of the hard register. Otherwise it returns NO_REGS. */
static enum reg_class
single_reg_operand_class (int op_num)
{
if (op_num < 0 || recog_data.n_alternatives == 0)
return NO_REGS;
return single_reg_class (recog_data.constraints[op_num],
recog_data.operand[op_num], NULL_RTX);
}
/* The function sets up hard register set *SET to hard registers which
might be used by insn reloads because the constraints are too
strict. */
void
ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
{
int i, curr_alt, c, regno = 0;
bool ignore_p;
enum reg_class cl;
rtx op;
enum machine_mode mode;
CLEAR_HARD_REG_SET (*set);
for (i = 0; i < recog_data.n_operands; i++)
{
op = recog_data.operand[i];
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
if (GET_CODE (op) == SCRATCH
|| (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
{
const char *p = recog_data.constraints[i];
mode = (GET_CODE (op) == SCRATCH
? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
cl = NO_REGS;
for (ignore_p = false, curr_alt = 0;
(c = *p);
p += CONSTRAINT_LEN (c, p))
if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
{
curr_alt++;
ignore_p = false;
}
else if (! ignore_p)
switch (c)
{
case 'r':
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
case 'h': case 'j': case 'k': case 'l':
case 'q': case 't': case 'u':
case 'v': case 'w': case 'x': case 'y': case 'z':
case 'A': case 'B': case 'C': case 'D':
case 'Q': case 'R': case 'S': case 'T': case 'U':
case 'W': case 'Y': case 'Z':
cl = (c == 'r'
? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c, p));
if (cl != NO_REGS)
{
/* There is no register pressure problem if all of the
regs in this class are fixed. */
int regno = ira_class_singleton[cl][mode];
if (regno >= 0)
add_to_hard_reg_set (set, mode, regno);
}
break;
}
}
}
}
/* Processes input operands, if IN_P, or output operands otherwise of
the current insn with FREQ to find allocno which can use only one
hard register and makes other currently living allocnos conflicting
with the hard register. */
static void
process_single_reg_class_operands (bool in_p, int freq)
{
int i, regno;
unsigned int px;
enum reg_class cl;
rtx operand;
ira_allocno_t operand_a, a;
for (i = 0; i < recog_data.n_operands; i++)
{
operand = recog_data.operand[i];
if (in_p && recog_data.operand_type[i] != OP_IN
&& recog_data.operand_type[i] != OP_INOUT)
continue;
if (! in_p && recog_data.operand_type[i] != OP_OUT
&& recog_data.operand_type[i] != OP_INOUT)
continue;
cl = single_reg_operand_class (i);
if (cl == NO_REGS)
continue;
operand_a = NULL;
if (GET_CODE (operand) == SUBREG)
operand = SUBREG_REG (operand);
if (REG_P (operand)
&& (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
{
enum reg_class aclass;
operand_a = ira_curr_regno_allocno_map[regno];
aclass = ALLOCNO_CLASS (operand_a);
if (ira_class_subset_p[cl][aclass])
{
/* View the desired allocation of OPERAND as:
(REG:YMODE YREGNO),
a simplification of:
(subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
enum machine_mode ymode, xmode;
int xregno, yregno;
HOST_WIDE_INT offset;
xmode = recog_data.operand_mode[i];