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HPS Baseline System Example Design for Agilex 3 FPGA and SoC C-Series Development Kit

This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 3 FPGA and SoC C-Series Development Kit.

Description

Agilex 3 GHRD is a reference design for Altera Agilex 3 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications. Refer to the HPS GSRD User Guide for the Agilex 3 C-Series Development Kit for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:

  • Hard Processor System (HPS) enablement and configuration
    • Enable dual core Arm Cortex-A55 processor
    • HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, I3C, JTAG, UART, and GPIO)
    • HPS Clock and Reset
    • HPS FPGA Bridge and Interrupt
      • Note: The System MMU port in F2SDRAM bridge is disabled by default
  • HPS EMIF configuration (Inline ECC for LPDDR4 is enabled by default)
  • System integration with FPGA IPs
    • Fabric subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling PushButton and LEDs.
    • NiosV subsystem that consists of JTAG Avalon Master Bridge IP and Address Span Extender IP to allow System-Console debug activity and FPGA content access through JTAG.

Project Details

  • Family: Agilex 3
  • Quartus Version: 26.1
  • Development Kit: Agilex 3 FPGA and SoC C-Series Development Kit DK-A3W135BM16AEA
  • Device Part: A3CW135BM16AE6S
  • Category: HPS
  • Source: Quartus Prime Pro
  • URL: https://www.github.com/altera-fpga/agilex3c-ed-gsrd
  • Design Package: a3cw135-devkit-oobe-baseline.zip

Documentations

GHRD Overview

Note for *USB3.1: Agilex 3 Hard Processor System supports USB3.1. However, Agilex 3 FPGA and SoC C-Series Development Kit does not have transceiver (XCVR) for USB3.1. Therefore, the board only supports USB 2.0 ULPI interface via USB 3.1 controller. GHRD_overview

Hard Processor System (HPS)

The GHRD HPS configuration matches the board schematic. Refer to Hard Processor System Technical Reference Manual: Agilex 3 SoCs and Hard Processor System Component Reference Manual: Agilex 3 SoCs for more information on HPS configuration.

HPS External Memory Interfaces (EMIF)

The GHRD HPS EMIF configuration matches the board schematic. Refer to External Memory Interfaces (EMIF) IP User Guide: Agilex 3 FPGAs and SoCs for more information on HPS EMIF configuration.

Bridges

Bridges are used to move data between FPGA fabric and HPS logic. Refer to HPS Bridges

The HPS address map and the FPGA address map are the same for Agilex 3. Refer to Total Address Map Graphical for more information.

Therefore, when accessing HPS logic in uboot or linux, the base address would be the same as, when using Debug Subsystem from FPGA fabric.

Bridge Use Case
F2SDRAM move data from FPGA fabric to HPS logic (non-coherent). Can access HPS EMIF.
LWH2F move data from HPS logic to FPGA fabric. Access FPGA peripherial Control Status Register (CSR).
H2F move data from HPS logic to FPGA fabric. Access FPGA Onchip Memory as scratch pad.

Fabric Subsystem

NiosV Subsystem

The GHRD JTAG UART IP interfaces allows you to access peripherals in the FPGA with System Console, through the JTAG UART IP module. This access does not rely on HPS software drivers.

Refer to this Guide for information about system console.

Peripheral

Peripheral Address Offset Size (bytes) Attribute Interrupt Number
sysid 0x0001_0000 8 Unique system ID None
led_pio 0x0001_0080 16 LED outputs None
button_pio 0x0001_0060 16 Push button inputs 1

Notes

  • There are 1 user push-button inputs and 2 LED outputs that is connected to fpga pins on Agilex 3 FPGA and SoC C-Series Development Kit.
    • Only the lower bit of LED outputs are available for software to control. The most significant bit of the LED is used in GHRD top module as heartbeat led. This LED blinks when the fpga design is loaded. Users will not be able to control this LED with HPS software, for example U-Boot or Linux.
  • The peripherial is accessed via the LWH2F bridge and have offset of 0x0_2000_0000. Refer to Total Address Map Graphicals for more information.
  • The FPGA IRQ has offset of 17 when mapped to Generic Interrupt Controller (GIC) in device tree structure(dts). Refer to GIC Shared Peripheral Interrupts Map for the SoC HPS

GHRD Build

Prerequisites

  • Altera Quartus Prime 26.1
  • Python 3.11.5 (only required when using command line to build)

Using Quartus GUI

  1. Launch Quartus Prime 26.1.
  2. Open the design project. E.g top.qpf.
  3. Click the play button to compile the design.
  4. The compiled sof can be found in output_files folder of the project path.

Using Command Line

  1. Build the design sof
make baseline-build

After build, the bitstream (sof) can be found in output_files folder.

  1. Use the following command to generate the core.rbf (optional)
make baseline-install-core-rbf

The generated core.rbf can be found in install/binaries folder.

Yocto Build Setup Guide

  1. Refer to Yocto Linux Build Instructions file and follow the steps to build Yocto.

After build, the binaries can be found in the software/yocto_linux_sd or software/yocto_linux_qspi folder.

HPS Debug Program

Refer to the README file and follow the steps to build the HPS content wipe program.