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HPS Baseline-A76 System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit (ES)

HPS Baseline-A76 System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.

Description

Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\n Refer to the Agilex 5 E-Series Premium Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode and boots from Arm Cortex-A76 core 2 processor.

Baseline-A76 feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:

  • Hard Processor System (HPS) enablement and configuration
    • Enable dual core Arm Cortex-A76 processor
    • Enable dual core Arm Cortex-A55 processor
    • HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)
    • HPS Clock and Reset
    • HPS FPGA Bridge and Interrupt
      • Note: The System MMU port in F2H and F2SDRAM bridges are disabled by default
  • HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)
  • System integration with FPGA IPs
    • Fabric subsystem that consists of NiosV subsystem, 256KB of FPGA On-Chip Memory, System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs.
    • NiosV subsystem that consists of JTAG Avalon Master Bridge IP and Address Span Extender IP to allow System-Console debug activity and FPGA content access through JTAG.

USB modes

This design supports USB 3.1 in both host and device mode.
Once power up, the USB mode will remain and cannot be changed during runtime.

The linux device tree (dts) needs to be configured.
The dts can be set with "dr_mode".

dr_mode valueEquivalent USB mode
hostHost
peripheralDevice

Project Details

Documentations

GHRD Overview

Block Diagram Baseline-A76 GHRD Overview

Hard Processor System (HPS)

The GHRD HPS configuration matches the board schematic. Refer to Agilex 5 Hard Processor System Technical Reference Manual and Hard Processor System Component Reference Manual: Agilex 5 SoCs for more information on HPS configuration.

HPS External Memory Interfaces (EMIF) DDR

The GHRD HPS EMIF DDR configuration matches the board schematic. Refer to External Memory Interfaces (EMIF) IP User Guide: Agilex 5 FPGAs and SoCs for more information on HPS EMIF configuration.

Bridges

Bridges are used to move data between FPGA fabric and HPS logic. Refer to HPS Bridges.

The HPS address map and the FPGA address map are the same for Agilex 5. Refer to Total Address Map Graphical for more information.

Therefore, when accessing HPS logic in uboot or linux, the base address would be the same as, when using NiosV Subsystem from FPGA fabric.

Bridge Use Case
F2SDRAM move data from FPGA fabric to HPS logic (non-coherent). Can access HPS EMIF.
F2S move data from FPGA fabric to HPS logic (coherent). Can access all HPS peripherial except the GIC.
LWS2F move data from HPS logic to FPGA fabric. Access FPGA peripherial Control Status Register (CSR).
H2F move data from HPS logic to FPGA fabric. Access FPGA Onchip Memory as scratch pad.

Fabric Subsystem

NiosV Subsystem

In the NiosV subsystem, the JTAG Avalon Master Bridge IP interface allows access to the peripherals in the FPGA with System Console. This access does not rely on HPS software drivers. Refer to this Guide for information about system console.

Peripherals

Peripheral Address Offset Size (bytes) Attribute Interrupt Number
sysid 0x0001_0000 8 Unique system ID None
led_pio 0x0001_0080 16 LED outputs None
button_pio 0x0001_0060 16 Push button inputs 0
dipsw_pio 0x0001_0070 16 DIP switch inputs None

Notes

  • There are 4 user DIP switch inputs, 4 user push-button inputs and 4 LED outputs that is connected to fpga pins on Agilex 5 FPGA E-Series 065B Premium Development Kit.
    • Only the lower three bits of LED outputs are available for software to control. The most significant bit of the LED is used in GHRD top module as heartbeat led. This LED blinks when the fpga design is loaded. Users will not be able to control this LED with HPS software, for example U-Boot or Linux.
  • The peripheral components in fabric subsystem can be accessed via the LWS2F bridge and have offset of 0x0_2000_0000. Refer to Total Address Map Graphical.
  • The FPGA IRQ has offset of 17 when mapped to Generic Interrupt Controller (GIC) in device tree structure(dts). Refer to fpga2hps_interrupt_irq0[0] in GIC Shared Peripheral Interrupts Map for the SoC HPS.

GHRD Build

Prerequisites

  • Altera Quartus Prime 26.1
  • Python 3.11.5 (only required when using command line to build)

Using Quartus GUI

  1. Launch Quartus Prime 26.1.
  2. Open the design project. E.g top.qpf.
  3. Click the play button to compile the design.
  4. The compiled sof can be found in output_files folder of the project path.

Using Command Line

  1. Build the design sof
make baseline_a76-build

After build, the bitstream (sof) can be found in output_files folder.

  1. Use the following command to generate the core.rbf (optional)
make baseline_a76-install-core-rbf

The generated core.rbf can be found in install/binaries folder.

GHRD simulation

Follow the steps below to simulate the design using the testbench located in the design sim folder:

  1. Prepare simulation scripts In the current project directory, run the following command to generate the necessary simulation scripts for QuestaSim, VCS (3-step), and Xcelium from Quartus:
make baseline_a76-prep
  1. Run the Simulation Navigate to the sim directory
cd sim

Depending on your simulator, execute the appropriate shell script to start the simulation. For example: For VCS (3-step) simulator,

./runvcs.sh

For QuestaSim and Questa FE simulator,

./runquesta.sh

For Xcelium simulator,

./runxcelium.sh

Yocto Build Setup Guide

  1. Refer to Yocto Linux Build Instructions file and follow the steps to build Yocto.

After build, the binaries can be found in the software/yocto_linux_sd or software/yocto_linux_qspi folder.

HPS Debug Program

Refer to the README file and follow the steps to build the HPS content wipe program.