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g431: added CANFD driver
1 parent 4f63947 commit 186cc3c

5 files changed

Lines changed: 467 additions & 12 deletions

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Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ ROOT := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
2020
include $(ROOT)/make/tools.mk
2121

2222
# MCU builds, if with _xxK then adds build with given flash size
23-
MCU_BUILDS := E230 F031 F051 F415 F415_128K F421 G071 G071_64K L431 L431_128K G431 V203 L431_CAN F415_CAN
23+
MCU_BUILDS := E230 F031 F051 F415 F415_128K F421 G071 G071_64K L431 L431_128K G431 V203 L431_CAN F415_CAN G431_CAN
2424

2525
# we support bootloader comms on a list of possible pins
2626
BOOTLOADER_PINS = PB4 PA2 PA6 PA15 PA0

Mcu/g431/Inc/blutil.h

Lines changed: 25 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,9 @@
1717
/*
1818
we have up to 512k of flash, but only use 64k for now
1919
*/
20+
#ifndef BOARD_FLASH_SIZE
2021
#define BOARD_FLASH_SIZE 64
22+
#endif
2123

2224
#define GPIO_PIN(n) (1U<<(n))
2325

@@ -27,6 +29,7 @@
2729

2830
#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL
2931

32+
#ifdef PORT_LETTER
3033
static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down)
3134
{
3235
LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_INPUT);
@@ -53,6 +56,7 @@ static inline bool gpio_read(uint32_t pin)
5356
{
5457
return LL_GPIO_IsInputPinSet(input_port, pin);
5558
}
59+
#endif // PORT_LETTER
5660

5761
#define BL_TIMER TIM2
5862

@@ -102,28 +106,37 @@ static inline void bl_clock_config(void)
102106
while (LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4) ;
103107
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
104108
while (LL_PWR_IsActiveFlag_VOS() != 0) ;
105-
106109
LL_RCC_HSI_Enable();
107-
108-
/* Wait till HSI is ready */
109110
while (LL_RCC_HSI_IsReady() != 1) ;
110111

112+
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
113+
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
114+
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
115+
111116
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_2, 40, LL_RCC_PLLR_DIV_2);
112117
LL_RCC_PLL_EnableDomain_SYS();
113-
LL_RCC_PLL_Enable();
114118

115-
/* Wait till PLL is ready */
119+
#if DRONECAN_SUPPORT
120+
LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL);
121+
LL_RCC_PLL_EnableDomain_48M();
122+
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, LL_RCC_PLLQ_DIV_4);
123+
124+
// also enable the backup domain registers in TAMP for communication
125+
// between bootloader and main firmware
126+
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
127+
PWR->CR1 |= PWR_CR1_DBP;
128+
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_NONE);
129+
RCC->BDCR |= RCC_BDCR_RTCEN;
130+
#endif
131+
132+
LL_RCC_PLL_Enable();
116133
while (LL_RCC_PLL_IsReady() != 1) ;
117-
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
118134

119-
/* Wait till System clock is ready */
135+
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
120136
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) ;
121-
122-
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
123-
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
124-
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
125137
}
126138

139+
#ifdef PORT_LETTER
127140
static inline void bl_gpio_init(void)
128141
{
129142
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
@@ -180,3 +193,4 @@ static inline void jump_to_application(void)
180193
void SystemInit()
181194
{
182195
}
196+
#endif // PORT_LETTER

bootloader/DroneCAN/DroneCAN.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@
3232
#define DRONECAN_DEBUG 0
3333
#endif
3434

35+
#ifndef DRONECAN_CHECK_SIGNATURE
36+
#define DRONECAN_CHECK_SIGNATURE 1
37+
#endif
38+
3539
// assume that main fw starts at 16k
3640
#define MAIN_FW_START_ADDR 0x08004000
3741

@@ -147,6 +151,7 @@ static const uint8_t default_settings[] = {
147151
0x80, 0x80, 0x80, 0x32, 0x00, 0x32, 0x00, 0x00, 0x0f, 0x0a, 0x0a, 0x8d, 0x66, 0x06, 0x00, 0x00
148152
};
149153

154+
#if DRONECAN_CHECK_SIGNATURE
150155
// crc32 implementation, slow method for small flash cost
151156
static uint32_t crc32(const uint8_t *buf, uint32_t size)
152157
{
@@ -162,6 +167,7 @@ static uint32_t crc32(const uint8_t *buf, uint32_t size)
162167
}
163168
return crc;
164169
}
170+
#endif
165171

166172
// print to CAN LogMessage for debugging
167173
static void can_print(const char *s)
@@ -864,6 +870,8 @@ bool DroneCAN_boot_ok(void)
864870
set_reason(FAIL_REASON_BAD_BOARD_ID, "bad board type");
865871
return false;
866872
}
873+
874+
#if DRONECAN_CHECK_SIGNATURE
867875
const uint8_t *appsigend = (const uint8_t *)(appsig+1);
868876
const uint32_t crc1 = crc32(fw_base, (uint32_t)((uint8_t*)appsig - fw_base));
869877
const uint32_t crc2 = crc32(appsigend, appsig->fwlen - (uint32_t)(appsigend - fw_base));
@@ -872,6 +880,7 @@ bool DroneCAN_boot_ok(void)
872880
set_reason(FAIL_REASON_BAD_CRC, "bad firmware CRC");
873881
return false;
874882
}
883+
#endif
875884

876885
if (!have_raw_command) {
877886
set_reason(FAIL_REASON_BAD_CRC, "no signal");

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