test: make nmigen 0.3+ compatible

and bump minimum nmigen version to 0.2

Author: rroohhh

nmigen_soc/test/test_csr_bus.py

@@ -240,9 +240,10 @@ def sim_test():
             self.assertEqual((yield elem_16_rw.w_stb), 1)
             self.assertEqual((yield elem_16_rw.w_data), 0xaa55)
 
-        with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
 
@@ -299,9 +300,10 @@ def sim_test():
             self.assertEqual((yield elem_20_rw.w_stb), 1)
             self.assertEqual((yield elem_20_rw.w_data), 0x3aa55)
 
-        with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
 
@@ -398,7 +400,8 @@ def sim_test():
 
         m = Module()
         m.submodules += self.dut, mux_1, mux_2
-        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(m)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()

nmigen_soc/test/test_csr_event.py

@@ -9,9 +9,10 @@
 
 
 def simulation_test(dut, process):
-    with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-        sim.add_clock(1e-6)
-        sim.add_sync_process(process)
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(process)
+    with sim.write_vcd(vcd_file=open("test.vcd", "w")):
         sim.run()
 
 

nmigen_soc/test/test_csr_wishbone.py

@@ -135,9 +135,10 @@ def sim_test():
 
         m = Module()
         m.submodules += mux, reg_1, reg_2, dut
-        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(m)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_wide(self):
@@ -222,7 +223,8 @@ def sim_test():
 
         m = Module()
         m.submodules += mux, reg, dut
-        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(m)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()

nmigen_soc/test/test_event.py

@@ -8,9 +8,10 @@
 
 
 def simulation_test(dut, process):
-    with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-        sim.add_clock(1e-6)
-        sim.add_sync_process(process)
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(process)
+    with sim.write_vcd(vcd_file=open("test.vcd", "w")):
         sim.run()
 
 

nmigen_soc/test/test_wishbone_bus.py

@@ -238,8 +238,9 @@ def sim_test():
             self.assertEqual((yield dut.bus.stall), 1)
             self.assertEqual((yield dut.bus.dat_r), 0x5678abcd)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_addr_translate(self):
@@ -348,8 +349,9 @@ def sim_test():
 
         m = Module()
         m.submodules += dut, loop_1, loop_2, loop_3, loop_4
-        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_process(sim_test())
+        sim = Simulator(m)
+        sim.add_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_coarse_granularity(self):
@@ -369,8 +371,9 @@ def sim_test():
             yield Delay(1e-6)
             self.assertEqual((yield sub.cyc), 0)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
 
@@ -475,9 +478,10 @@ def sim_test():
             self.assertEqual((yield intr_2.rty), 1)
             self.assertEqual((yield intr_2.stall), 0)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_lock(self):
@@ -526,9 +530,10 @@ def sim_test():
             self.assertEqual((yield intr_1.ack), 0)
             self.assertEqual((yield intr_2.ack), 1)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_stall(self):
@@ -551,8 +556,9 @@ def sim_test():
             self.assertEqual((yield intr_1.stall), 1)
             self.assertEqual((yield intr_2.stall), 1)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_stall_compat(self):
@@ -574,8 +580,9 @@ def sim_test():
             self.assertEqual((yield intr_1.stall), 0)
             self.assertEqual((yield intr_2.stall), 1)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
 
     def test_roundrobin(self):
@@ -633,7 +640,8 @@ def sim_test():
             self.assertEqual((yield intr_2.ack), 0)
             self.assertEqual((yield intr_3.ack), 1)
 
-        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            sim.add_sync_process(sim_test())
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_sync_process(sim_test)
+        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()

setup.py

@@ -23,7 +23,7 @@ def local_scheme(version):
     #long_description="""TODO""",
     license="BSD",
     setup_requires=["wheel", "setuptools", "setuptools_scm"],
-    install_requires=["nmigen>=0.1,<0.5"],
+    install_requires=["nmigen>=0.2,<0.5"],
     packages=find_packages(),
     project_urls={
         "Source Code": "https://github.com/nmigen/nmigen-soc",