diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py
index 5332f572d..02dbbaa3b 100644
--- a/amaranth/build/plat.py
+++ b/amaranth/build/plat.py
@@ -120,16 +120,22 @@ def create_missing_domain(self, name):
         # Many device families provide advanced primitives for tackling reset. If these exist,
         # they should be used instead.
         if name == "sync" and self.default_clk is not None:
-            clk_i = self.request(self.default_clk).i
+            m = Module()
+
+            clk_io = self.request(self.default_clk, dir="-")
+            m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
             else:
                 rst_i = Const(0)
 
-            m = Module()
             m.domains += ClockDomain("sync")
-            m.d.comb += ClockSignal("sync").eq(clk_i)
+            m.d.comb += ClockSignal("sync").eq(clk_buf.i)
             m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
+
             return m
 
     def prepare(self, elaboratable, name="top", **kwargs):
diff --git a/amaranth/vendor/_gowin.py b/amaranth/vendor/_gowin.py
index 280d009ef..08a43186e 100644
--- a/amaranth/vendor/_gowin.py
+++ b/amaranth/vendor/_gowin.py
@@ -532,10 +532,14 @@ def create_missing_domain(self, name):
                                              o_OSCOUT=clk_i)
 
             else:
-                clk_i = self.request(self.default_clk).i
+                clk_io = self.request(self.default_clk, dir="-")
+                m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+                clk_i = clk_buf.i
 
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
             else:
                 rst_i = Const(0)
 
diff --git a/amaranth/vendor/_lattice.py b/amaranth/vendor/_lattice.py
index 051460583..a0cea69cf 100644
--- a/amaranth/vendor/_lattice.py
+++ b/amaranth/vendor/_lattice.py
@@ -956,9 +956,14 @@ def create_missing_domain(self, name):
                     o_HFCLKOUT=clk_i,
                 )
             else:
-                clk_i = self.request(self.default_clk).i
+                clk_io = self.request(self.default_clk, dir="-")
+                m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+                clk_i = clk_buf.i
+
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
             else:
                 rst_i = Const(0)
 
diff --git a/amaranth/vendor/_quicklogic.py b/amaranth/vendor/_quicklogic.py
index 02d5af9df..c7809b9a6 100644
--- a/amaranth/vendor/_quicklogic.py
+++ b/amaranth/vendor/_quicklogic.py
@@ -1,6 +1,7 @@
 from abc import abstractmethod
 
 from ..hdl import *
+from ..lib import io
 from ..lib.cdc import ResetSynchronizer
 from ..build import *
 
@@ -172,10 +173,14 @@ def create_missing_domain(self, name):
                                          o_A=sys_clk0,
                                          o_Z=clk_i)
             else:
-                clk_i = self.request(self.default_clk).i
+                clk_io = self.request(self.default_clk, dir="-")
+                m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+                clk_i = clk_buf.i
 
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
             else:
                 rst_i = Const(0)
 
diff --git a/amaranth/vendor/_siliconblue.py b/amaranth/vendor/_siliconblue.py
index 690d7fbf2..bd5f99855 100644
--- a/amaranth/vendor/_siliconblue.py
+++ b/amaranth/vendor/_siliconblue.py
@@ -393,11 +393,15 @@ def create_missing_domain(self, name):
                 delay = int(100e-6 * self.default_clk_frequency)
             # User-defined clock signal.
             else:
-                clk_i = self.request(self.default_clk).i
+                clk_io = self.request(self.default_clk, dir="-")
+                m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+                clk_i = clk_buf.i
                 delay = int(15e-6 * self.default_clk_frequency)
 
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
             else:
                 rst_i = Const(0)
 
diff --git a/amaranth/vendor/_xilinx.py b/amaranth/vendor/_xilinx.py
index df73129db..02adfffcf 100644
--- a/amaranth/vendor/_xilinx.py
+++ b/amaranth/vendor/_xilinx.py
@@ -1144,11 +1144,16 @@ def create_missing_domain(self, name):
             return super().create_missing_domain(name)
 
         if name == "sync" and self.default_clk is not None:
-            clk_i = self.request(self.default_clk).i
+            m = Module()
+
+            clk_io = self.request(self.default_clk, dir="-")
+            m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
+            clk_i = clk_buf.i
             if self.default_rst is not None:
-                rst_i = self.request(self.default_rst).i
+                rst_io = self.request(self.default_rst, dir="-")
+                m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
+                rst_i = rst_buf.i
 
-            m = Module()
             ready = Signal()
             m.submodules += Instance(STARTUP_PRIMITIVE[self.family], o_EOS=ready)
             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)