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1 parent 503df5b commit 2ff1cc7Copy full SHA for 2ff1cc7
src/app.tsx
@@ -273,7 +273,7 @@ function AppContent() {
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</li>
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<li>
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<code>amaranth_playground.show_rtlil(rtlil.convert(m))</code> displays <Link
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- href="https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_Overview.html#the-rtl-intermediate-language-rtlil"
+ href="https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/rtlil_rep.html"
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>RTLIL code</Link>, the <Link href="https://yosyshq.net">Yosys</Link> intermediate
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representation. This code is accepted by the open-source FPGA toolchain, and is used
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internally by the Amaranth compiler to produce Verilog code. Unless you are investigating
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