FP16 Postop Support (#512)

- The postop support for Pure FP16 follow a partial-Spill approach to accommodate register pressure
------------------------------------------------------
AMD Internal : [SWLCGS-4198]
Signed-off-by: John Alexander <joalexan_amdeng@amd.com>

Author: amd-joalexan

classic/aocl_gemm_f16f16f16of16.c

@@ -257,15 +257,6 @@ aocl_gemm_f16f16f16of16(const char      order,
     dlp_param_map_char_to_lpmtag(mem_format_a, &mtag_a);
     dlp_param_map_char_to_lpmtag(mem_format_b, &mtag_b);
 
-    // Post-ops are not supported for FP16 GEMM.
-    // Check if any post-ops are specified and return error if so.
-    if ((metadata != NULL) && (metadata->seq_length > 0)) {
-        dlp_print_msg(" Post-ops are not supported for f16f16f16of16 gemm.",
-                      __FILE__, __LINE__);
-        DLP_METADATA_SET_ERROR(metadata, DLP_CLSC_NOT_SUPPORTED);
-        goto err_hndl;
-    }
-
     // Check for A-dequantization post-op (a_post_quant)
     if ((metadata != NULL) && (metadata->a_post_quant != NULL)) {
         dlp_print_msg(" A-dequantization post-op is not supported for "

classic/frame/dlp_gemm_post_ops.c

@@ -41,6 +41,9 @@ dlp_gemm_get_stor_type(DLP_TYPE pstor_type)
         case DLP_BF16:
             stor_type = DLP_BF16;
             break;
+        case DLP_F16:
+            stor_type = DLP_F16;
+            break;
         case DLP_S8:
             stor_type = DLP_S8;
             break;

classic/frame/fp16fp16fp16/dlp_gemm_fp16.c

@@ -98,7 +98,7 @@ DLP_GEMV(float16, float16, float16, f16f16f16of16)
     post_ops_attr.b_col_sum_vec     = NULL;
     post_ops_attr.b_col_sum_vec_s16 = NULL;
 
-    post_ops_attr.buf_downscale = NULL;
+    post_ops_attr.buf_downscale = c;
 
     /* Generate thrinfo objects for jc and ic loops */
     dlp_task_id_t thread_jc;
@@ -360,7 +360,7 @@ DLP_GEMM_5LOOP_UNIFIED(float16, float16, float16, float16, f16f16f16of16,
     post_ops_attr.b_sum_offset      = 0;
     post_ops_attr.b_col_sum_vec     = NULL;
     post_ops_attr.b_col_sum_vec_s16 = NULL;
-    post_ops_attr.buf_downscale     = NULL;
+    post_ops_attr.buf_downscale     = c;
 
     dlp_task_id_t thread_jc;
     dlp_task_id_t thread_ic;

src/jit/amdzen/amdzen_generator.cc

@@ -3003,6 +3003,16 @@ jitAmdZenFP16::executeKernel(dlp::kernels::kernelParams* _params)
                 params->nmask_fp16_avx512 =
                     0xFFFFFFFFu >> (numElemsPerReg - partial_elements);
             }
+
+            // F32 postops mask: 16 F32 elements per ZMM
+            static constexpr int F32_PER_ZMM = 16;
+            int                  f32_partial = params->n_left % F32_PER_ZMM;
+            if (f32_partial == 0) {
+                params->nmask_avx512 = 0xFFFFu;
+            } else {
+                params->nmask_avx512 = static_cast<uint16_t>(
+                    0xFFFFu >> (F32_PER_ZMM - f32_partial));
+            }
         }
 
         // Deploy the associated kernel based on n_left