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projects/adaq23875: Add adaq2387x support
Signed-off-by: Stanca Pop <[email protected]>
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‎projects/adaq23875/Makefile‎

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####################################################################################
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## Copyright (c) 2018 - 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk

‎projects/adaq23875/README.md‎

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# ADAQ2387X HDL Project
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- Evaluation board product page:
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- [EVAL-ADAQ23878](https://analog.com/eval-adaq23878)
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- [EVAL-ADAQ23876](https://analog.com/eval-adaq23876)
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- [EVAL-ADAQ23875](https://analog.com/eval-adaq23875)
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- System documentation: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577
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- HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/cn0577/index.html
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- Evaluation board VADJ: 2.5V
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## Supported parts
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| Part name | Description |
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|-----------------------------------------------|----------------------------------------------------|
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| [ADAQ23878](https://www.analog.com/ADAQ23878) | 18-Bit, 15 MSPS, μModule Data Acquisition Solution |
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| [ADAQ23876](https://www.analog.com/ADAQ23876) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution |
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| [ADAQ23875](https://www.analog.com/ADAQ23875) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/adaq23875/common/adaq23875_bd.tcl‎

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###############################################################################
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## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# env params
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set TWOLANES $ad_project_params(TWOLANES); # two-lane mode (1) or one-lane mode (0); default two-lane
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set ADC_RES $ad_project_params(ADC_RES); # ADC resolution: (18) or (16); default 18 bits
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set USE_MMCM $ad_project_params(USE_MMCM); # ref_clk frequency: 120MHz (1) or 100MHz (0); default 0
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set OUT_RES [expr {$ADC_RES == 16 ? 16 : 32}]
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set CLK_GATE_WIDTH [expr {($TWOLANES == 0 && $ADC_RES == 18) ? 9 : \
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($TWOLANES == 0 && $ADC_RES == 16) ? 8 : \
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($TWOLANES == 1 && $ADC_RES == 18) ? 5 : \
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4}]
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# adaq23875 i/o
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create_bd_port -dir I ref_clk
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create_bd_port -dir O sampling_clk
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create_bd_port -dir I dco_p
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create_bd_port -dir I dco_n
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create_bd_port -dir O cnv
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create_bd_port -dir I da_p
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create_bd_port -dir I da_n
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create_bd_port -dir I db_p
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create_bd_port -dir I db_n
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create_bd_port -dir O clk_gate
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# adc peripheral
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ad_ip_instance axi_ltc2387 axi_ltc2387
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ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES $ADC_RES
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ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES $OUT_RES
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ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $TWOLANES
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ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27
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# axi pwm gen
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ad_ip_instance axi_pwm_gen axi_pwm_gen
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ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2
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# pwm0 - cnv
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8
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# pwm1 - clk_gate
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH $CLK_GATE_WIDTH
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0
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# dma
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ad_ip_instance axi_dmac axi_ltc2387_dma
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ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC $OUT_RES
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ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# clk wizard
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if {$USE_MMCM == "1"} {
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create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
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set_property -dict [list \
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CONFIG.PRIM_IN_FREQ {100.000} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {120.000} \
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] [get_bd_cells clk_wiz_0]
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ad_connect ref_clk clk_wiz_0/clk_in1
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ad_connect sys_rstgen/peripheral_reset clk_wiz_0/reset
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ad_connect clk_wiz_0/clk_out1 sampling_clk
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ad_connect clk_wiz_0/clk_out1 axi_ltc2387/ref_clk
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ad_connect clk_wiz_0/clk_out1 axi_ltc2387_dma/fifo_wr_clk
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ad_connect clk_wiz_0/clk_out1 axi_pwm_gen/ext_clk
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} else {
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ad_connect ref_clk sampling_clk
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ad_connect ref_clk axi_ltc2387/ref_clk
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ad_connect ref_clk axi_ltc2387_dma/fifo_wr_clk
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ad_connect ref_clk axi_pwm_gen/ext_clk
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}
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# connections
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ad_connect sys_200m_clk axi_ltc2387/delay_clk
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ad_connect clk_gate axi_ltc2387/clk_gate
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ad_connect dco_p axi_ltc2387/dco_p
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ad_connect dco_n axi_ltc2387/dco_n
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ad_connect da_p axi_ltc2387/da_p
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ad_connect da_n axi_ltc2387/da_n
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if {$TWOLANES == "1"} {
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ad_connect db_p axi_ltc2387/db_p
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ad_connect db_n axi_ltc2387/db_n
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}
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ad_connect axi_ltc2387/adc_valid axi_ltc2387_dma/fifo_wr_en
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ad_connect axi_ltc2387/adc_data axi_ltc2387_dma/fifo_wr_din
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ad_connect axi_ltc2387/adc_dovf axi_ltc2387_dma/fifo_wr_overflow
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ad_connect cnv axi_pwm_gen/pwm_0
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ad_connect clk_gate axi_pwm_gen/pwm_1
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ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
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ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
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# address mapping
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ad_cpu_interconnect 0x44A00000 axi_ltc2387
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ad_cpu_interconnect 0x44A30000 axi_ltc2387_dma
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ad_cpu_interconnect 0x44A60000 axi_pwm_gen
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# interconnect (adc)
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_ltc2387_dma/m_dest_axi
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ad_connect $sys_cpu_resetn axi_ltc2387_dma/m_dest_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_ltc2387_dma/irq

‎projects/adaq23875/zed/Makefile‎

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####################################################################################
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## Copyright (c) 2018 - 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := adaq23875_zed
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../adaq23875/common/adaq23875_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_ltc2387
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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include ../../scripts/project-xilinx.mk

‎projects/adaq23875/zed/README.md‎

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<!-- no_no_os -->
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# ADAQ23875/ZED HDL Project
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- VADJ with which it was tested in hardware: 2.5V
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## Building the project
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The parameters configurable through the ``make`` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/adaq23875/zed
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make
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```
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The overwritable parameters from the environment are:
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- TWOLANES: whether to use two lanes or one lane mode;
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- 1 - two-lane mode used (default)
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- 0 - one-lane mode used
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- ADC_RES: the resolution of the ADC input data;
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- 18 - the resolution is 18 bits (default)
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- 16 - the resolution is 16 bits
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- USE_MMCM: choose between default 100MHz ref_clk or 120MHz
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- 1 - 120Mhz
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- 0 - 100MHz (default)
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### Example configurations
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#### Two lanes, 18-bit resolution, 100MHz ref_clk (default)
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This specific command is equivalent to running `make` only:
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```
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make TWOLANES=1 \
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ADC_RES=18 \
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USE_MMCM=0
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```
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Corresponding device tree: [zynq-zed-adv7511-adaq23878.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23878.dts)
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#### One lane, 18-bit resolution
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```
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make TWOLANES=0 \
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ADC_RES=18
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```
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#### Two lanes, 16-bit resolution
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```
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make TWOLANES=1 \
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ADC_RES=16
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```
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Corresponding device tree: [zynq-zed-adv7511-adaq23875.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23875.dts)
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#### One lane, 16-bit resolution
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```
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make TWOLANES=0 \
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ADC_RES=16
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```

‎projects/adaq23875/zed/system_bd.tcl‎

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###############################################################################
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## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# sourcing the common design
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source $ad_hdl_dir/projects/adaq23875/common/adaq23875_bd.tcl
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# system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "TWOLANES=$ad_project_params(TWOLANES) \
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ADC_RES=$ad_project_params(ADC_RES) \
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USE_MMCM=$ad_project_params(USE_MMCM)"
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sysid_gen_sys_init_file $sys_cstring

‎projects/adaq23875/zed/system_constr.xdc‎

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###############################################################################
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## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# adaq23875/adaq23876/adaq23878
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# clocks
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set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## G2 FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35
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set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
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# fpga_cnv
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en] ; ## G10 FMC_LA03_N IO_L16N_T2_34
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# dco, da, db
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_p] ; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34
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set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_n] ; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_p] ; ## H7 FMC_LA02_P IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_n] ; ## H8 FMC_LA02_N IO_L20N_T3_34
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_p] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_n] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34
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# 100MHz clock
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set clk_period 10
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# differential propagation delay for ref_clk
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set tref_early 0.3
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set tref_late 1.5
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# clocks
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create_clock -period $clk_period -name ref_clk [get_ports ref_clk_p]
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# clock latencies
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# minimum source latency values
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set_clock_latency -source -early $tref_early [get_clocks ref_clk]
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# maximum source latency values
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set_clock_latency -source -late $tref_late [get_clocks ref_clk]

‎projects/adaq23875/zed/system_project.tcl‎

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###############################################################################
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## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# load scripts
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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# TWOLANES: parameter describing the number of lanes
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# - 1: in two-lane mode (default)
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# - 0: in one-lane mode
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#
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# ADC_RES: parameter describing the ADC input resolution, thus selecting
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# between ADAQ23878 (18-bit, default) and ADAQ23875/ADAQ23876 (16-bit)
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# - 18: 18 bits, ADAQ23878 (default)
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# - 16: 16 bits, ADAQ23875 & ADAQ23876
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#
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# USE_MMCM: parameter used to select between the 100MHz ref_clk or passing it
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# through a clk_wizard and increase it to 120MHz
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# - 1: use the default clocking scheme
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# - 0: use the clk_wizard to increase the clk frequency
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#
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# The valid configurations for each supported evaluation board, depending on
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# the above parameters, are:
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#
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# Eval board | ADC_RES | TWOLANES | USE_MMCM |
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# ============================================
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# ADAQ23875 | 16 | 0 or 1 | 0 or 1 |
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# ADAQ23876 | 16 | 0 or 1 | 0 or 1 |
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# ADAQ23878 | 18 | 0 or 1 | 0 or 1 |
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adi_project adaq23875_zed 0 [list \
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TWOLANES [get_env_param TWOLANES 1 ] \
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ADC_RES [get_env_param ADC_RES 18 ] \
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USE_MMCM [get_env_param USE_MMCM 0 ]]
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# Base files
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set base_files [list \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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# Append timing constraint file based on USE_MMCM
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if { [get_env_param USE_MMCM 0] == 1 } {
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lappend base_files "timing_mmcm.xdc"
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} else {
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lappend base_files "timing_default.xdc"
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}
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# Register final list
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adi_project_files adaq23875_zed $base_files
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adi_project_run adaq23875_zed

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