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AndreiGrozavAndreiGrozav
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adrv9001: Update for mcs feature added on axi core
Update for added MCS feature on axi_adrv9001. Remove debuge ports on zcu102 Signed-off-by: AndreiGrozav <[email protected]>
1 parent f0cfb7a commit af2ec78

13 files changed

+80
-103
lines changed

‎projects/adrv9001/common/adrv9001_bd.tcl

-14
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,6 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# create debug ports
7-
create_bd_port -dir O adc1_div_clk
8-
create_bd_port -dir O adc2_div_clk
9-
create_bd_port -dir O dac1_div_clk
10-
create_bd_port -dir O dac2_div_clk
11-
126
create_bd_port -dir I tx_output_enable
137

148
create_bd_port -dir I ref_clk
@@ -313,11 +307,3 @@ ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq
313307
ad_cpu_interrupt ps-12 mb-11 axi_adrv9001_rx2_dma/irq
314308
ad_cpu_interrupt ps-9 mb-6 axi_adrv9001_tx1_dma/irq
315309
ad_cpu_interrupt ps-10 mb-5 axi_adrv9001_tx2_dma/irq
316-
317-
318-
# Connect debug ports
319-
ad_connect axi_adrv9001/adc_1_clk adc1_div_clk
320-
ad_connect axi_adrv9001/adc_2_clk adc2_div_clk
321-
ad_connect axi_adrv9001/dac_1_clk dac1_div_clk
322-
ad_connect axi_adrv9001/dac_2_clk dac2_div_clk
323-

‎projects/adrv9001/zc706/system_constr.xdc

+9-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -48,6 +48,14 @@ set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS18} [get_ports platform
4848

4949
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS18} [get_ports tdd_sync] ;#PMOD1_0 J58.1
5050

51+
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL18_II} [get_ports dev_mcs_fpga_out_p]
52+
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD DIFF_SSTL18_II} [get_ports dev_mcs_fpga_out_n]
53+
54+
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_p]
55+
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_n]
56+
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_p]
57+
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_n]
58+
5159
# set IOSTANDARD according to VADJ 1.8V
5260

5361
# hdmi

‎projects/adrv9001/zc706/system_top.v

+31-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2021-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -142,6 +142,13 @@ module system_top (
142142
output tx2_strobe_out_n,
143143
output tx2_strobe_out_p,
144144

145+
output dev_mcs_fpga_out_n,
146+
output dev_mcs_fpga_out_p,
147+
input fpga_mcs_in_n,
148+
input fpga_mcs_in_p,
149+
input fpga_ref_clk_p,
150+
input fpga_ref_clk_n,
151+
145152
inout sm_fan_tach,
146153
input vadj_err,
147154
output platform_status,
@@ -167,11 +174,29 @@ module system_top (
167174
wire tdd_sync_i;
168175
wire tdd_sync_cntr;
169176
wire mssi_sync;
177+
wire fpga_ref_clk;
178+
wire fpga_mcs_in;
179+
wire mcs_out;
170180

171181
// instantiations
172182

183+
OBUFDS i_obufds_dev_mcs_fpga_in (
184+
.I (mcs_out),
185+
.O (dev_mcs_fpga_out_p),
186+
.OB (dev_mcs_fpga_out_n));
187+
188+
IBUFDS i_ibufgs_fpga_ref_clk (
189+
.I (fpga_ref_clk_p),
190+
.IB (fpga_ref_clk_n),
191+
.O (fpga_ref_clk));
192+
193+
IBUFDS i_ibufgs_fpga_mcs_in (
194+
.I (fpga_mcs_in_p),
195+
.IB (fpga_mcs_in_n),
196+
.O (fpga_mcs_in));
197+
173198
// multi-ssi synchronization
174-
//
199+
175200
assign mssi_sync = gpio_o[54];
176201

177202
assign platform_status = vadj_err;
@@ -275,8 +300,11 @@ module system_top (
275300
.spi1_sdo_i (1'b0),
276301
.spi1_sdo_o (),
277302

278-
//FMC connections
279303
.mssi_sync (mssi_sync),
304+
//FMC connections
305+
.ref_clk (fpga_ref_clk),
306+
.mcs_in (fpga_mcs_in),
307+
.mcs_out (mcs_out),
280308

281309
.tx_output_enable (~vadj_err),
282310

‎projects/adrv9001/zcu102/lvds_constr.xdc

+19-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -47,10 +47,10 @@ set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS}
4747

4848
create_clock -name ref_clk -period 8.00 [get_ports fpga_ref_clk_p]
4949

50-
create_clock -name rx1_dclk_out -period 2.034 [get_ports rx1_dclk_in_p]
51-
create_clock -name rx2_dclk_out -period 2.034 [get_ports rx2_dclk_in_p]
52-
create_clock -name tx1_dclk_out -period 2.034 [get_ports tx1_dclk_in_p]
53-
create_clock -name tx2_dclk_out -period 2.034 [get_ports tx2_dclk_in_p]
50+
create_clock -name rx1_dclk_out -period 2.0 -waveform {0.0 1.0} [get_ports rx1_dclk_in_p]
51+
create_clock -name rx2_dclk_out -period 2.0 -waveform {0.0 1.0} [get_ports rx2_dclk_in_p]
52+
create_clock -name tx1_dclk_out -period 2.0 -waveform {0.0 1.0} [get_ports tx1_dclk_in_p]
53+
create_clock -name tx2_dclk_out -period 2.0 -waveform {0.0 1.0} [get_ports tx2_dclk_in_p]
5454

5555
# Allow max skew of 0.2 ns between input clocks
5656
set_clock_latency -source -early -0.1 [get_clocks rx1_dclk_out]
@@ -69,3 +69,17 @@ set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_2 \
6969
[get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast/O]] \
7070
]
7171

72+
set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_3 \
73+
[list [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_div_clk_buf/O}]] \
74+
[get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_clk_buf_fast/O}]] \
75+
]
76+
77+
set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_4 \
78+
[list [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_div_clk_buf/O}]] \
79+
[get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_clk_buf_fast/O}]] \
80+
]
81+
82+
set_input_delay -clock [get_clocks {ref_clk}] -min -add_delay 2.0 [get_ports {fpga_mcs_in_p}]
83+
set_input_delay -clock [get_clocks {ref_clk}] -max -add_delay 3.0 [get_ports {fpga_mcs_in_p}]
84+
85+
set_false_path -to [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_sync/mssi_sync_in_d_reg/D]

‎projects/adrv9001/zcu102/system_bd.tcl

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

‎projects/adrv9001/zcu102/system_constr.xdc

+1-13
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -49,15 +49,3 @@ set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p]
4949

5050
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports tdd_sync] ;#PMOD0_0 J55.1
5151

52-
# Debug port (Proto header)
53-
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports proto_hdr[0]] ;# J3 24 L8P_HDGC_50_P
54-
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports proto_hdr[1]] ;# J3 22 L8N_HDGC_50_N
55-
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[2]] ;# J3 20 L11P_AD9P_50_P
56-
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[3]] ;# J3 18 L11N_AD9N_50_N
57-
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[4]] ;# J3 16 L12P_AD8P_50_P
58-
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports proto_hdr[5]] ;# J3 14 L12N_AD8N_50_N
59-
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports proto_hdr[6]] ;# J3 12 L9P_AD11P_50_P
60-
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[7]] ;# J3 10 L9N_AD11N_50_N
61-
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[8]] ;# J3 8 L10P_AD10P_50_P
62-
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[9]] ;# J3 6 L10N_AD10N_50_N
63-

‎projects/adrv9001/zcu102/system_top.v

+3-14
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -124,10 +124,7 @@ module system_top (
124124
input vadj_err,
125125
output platform_status,
126126

127-
inout tdd_sync,
128-
129-
//debug hdr
130-
output [9:0] proto_hdr
127+
inout tdd_sync
131128
);
132129

133130
// internal registers
@@ -296,14 +293,6 @@ module system_top (
296293
.spi1_sclk (),
297294
.spi1_csn (),
298295
.spi1_miso (1'b0),
299-
.spi1_mosi (),
300-
301-
// debug
302-
.adc1_div_clk (proto_hdr[0]),
303-
.adc2_div_clk (proto_hdr[1]),
304-
.dac1_div_clk (proto_hdr[2]),
305-
.dac2_div_clk (proto_hdr[3]));
306-
307-
assign proto_hdr[9:4] = {'b0};
296+
.spi1_mosi ());
308297

309298
endmodule

‎projects/adrv9001/zed/system_constr.xdc

+9-30
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -21,35 +21,6 @@ set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports dgpio_9]
2121
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports dgpio_10] ; # H16 FMC_HPC0_LA11_P IO_L5P_T0_34
2222
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports dgpio_11] ; # C27 FMC_HPC0_LA27_N IO_L17N_T2_AD5N_35
2323

24-
set_property -dict {PACKAGE_PIN K19 IOSTANDARD DIFF_SSTL18_II} [get_ports fpga_mcs_out_p] ; ## C18 FMC_LPC_LA14_P
25-
set_property -dict {PACKAGE_PIN K20 IOSTANDARD DIFF_SSTL18_II} [get_ports fpga_mcs_out_n] ; ## C19 FMC_LPC_LA14_N
26-
27-
set_property OFFCHIP_TERM NONE [get_ports [list dev_mcs_fpga_out_p]]
28-
set_property is_loc_fixed true [get_ports [list dev_mcs_fpga_out_p]]
29-
set_property is_loc_fixed true [get_ports [list dev_mcs_fpga_out_n]]
30-
31-
set_property -dict {PACKAGE_PIN A21 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_p] ; ## H37 FMC_LPC_LA32_P
32-
set_property -dict {PACKAGE_PIN A22 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_n] ; ## H38 FMC_LPC_LA32_N
33-
set_property -dict {PACKAGE_PIN D18 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_p] ; ## G02 FMC_LPC_CLK1_M2C_P
34-
set_property -dict {PACKAGE_PIN C19 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_n] ; ## G03 FMC_LPC_CLK1_M2C_N
35-
36-
37-
# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports [list fpga_mcs_in_p]]
38-
# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports [list fpga_ref_clk_p]]
39-
# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports [list dev_mcs_fpga_out_p]]
40-
# set_property SLEW {} [get_ports [list dev_mcs_fpga_out_p]]
41-
# set_property OFFCHIP_TERM NONE [get_ports [list dev_mcs_fpga_out_p]]
42-
# set_property OFFCHIP_TERM NONE [get_ports [list fpga_mcs_in_p]]
43-
# set_property in_term UNTUNED_SPLIT_50 [get_ports [list fpga_mcs_in_p]]
44-
# set_property in_term UNTUNED_SPLIT_50 [get_ports [list fpga_ref_clk_p]]
45-
46-
# set_property in_term UNTUNED_SPLIT_50 [get_ports [list fpga_mcs_in_p]]
47-
# set_property in_term UNTUNED_SPLIT_50 [get_ports [list fpga_ref_clk_p]]
48-
# set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports [list fpga_ref_clk_p]]
49-
# set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports [list fpga_mcs_in_p]]
50-
# set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports [list dev_mcs_fpga_out_p]]
51-
52-
5324
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS18} [get_ports gp_int] ; # H34 FMC_HPC0_LA30_P IO_L7P_T1_AD2P_35
5425
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports mode] ; # D17 FMC_HPC0_LA13_P IO_L4P_T0_34
5526
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports reset_trx] ; # D18 FMC_HPC0_LA13_N IO_L4N_T0_34
@@ -70,6 +41,14 @@ set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports tx2_enabl
7041
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports vadj_err] ; # G33 FMC_HPC0_LA31_P IO_L8P_T1_AD10P_35
7142
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports platform_status] ; # G34 FMC_HPC0_LA31_N IO_L8N_T1_AD10N_35
7243

44+
set_property -dict {PACKAGE_PIN K19 IOSTANDARD DIFF_SSTL18_II} [get_ports dev_mcs_fpga_out_p] ; ## C18 FMC_LPC_LA14_P
45+
set_property -dict {PACKAGE_PIN K20 IOSTANDARD DIFF_SSTL18_II} [get_ports dev_mcs_fpga_out_n] ; ## C19 FMC_LPC_LA14_N
46+
47+
set_property -dict {PACKAGE_PIN A21 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_p] ; ## H37 FMC_LPC_LA32_P
48+
set_property -dict {PACKAGE_PIN A22 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_mcs_in_n] ; ## H38 FMC_LPC_LA32_N
49+
set_property -dict {PACKAGE_PIN D18 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_p] ; ## G02 FMC_LPC_CLK1_M2C_P
50+
set_property -dict {PACKAGE_PIN C19 IOSTANDARD DIFF_HSTL_II_18} [get_ports fpga_ref_clk_n] ; ## G03 FMC_LPC_CLK1_M2C_N
51+
7352
# redefine contraints from common file for VADJ 1.8V
7453
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports otg_vbusoc]
7554
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## BTNC

‎projects/adrv9001/zed/system_top.v

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -194,6 +194,7 @@ module system_top (
194194
wire tdd_sync_loc;
195195
wire tdd_sync_i;
196196
wire tdd_sync_cntr;
197+
wire mssi_sync;
197198
wire fpga_ref_clk;
198199
wire fpga_mcs_in;
199200
wire mcs_out;
@@ -329,11 +330,11 @@ module system_top (
329330
.iic_mux_sda_t (iic_mux_sda_t_s),
330331
.otg_vbusoc (otg_vbusoc),
331332
.spdif (spdif),
333+
.mssi_sync (mssi_sync),
332334
//FMC connections
333335
.ref_clk (fpga_ref_clk),
334336
.mcs_in (fpga_mcs_in),
335337
.mcs_out (mcs_out),
336-
.mssi_sync (mssi_sync),
337338

338339
.tx_output_enable (~vadj_err),
339340

‎projects/jupiter_sdr/system_bd.tcl

+1-17
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
################################################################################
55

@@ -650,19 +650,3 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
650650
set sys_cstring "USE_RX_CLK_FOR_TX1=$USE_RX_CLK_FOR_TX1,\
651651
USE_RX_CLK_FOR_TX2=$USE_RX_CLK_FOR_TX2"
652652
sysid_gen_sys_init_file $sys_cstring
653-
654-
### CRITICAL WARNING. Downgrade this critical warning to a simple warning.
655-
## rx1/rx2/tx1/tx2 dclk_out and ref_clk are input ports, there is no FPGA common node
656-
## between ref_clk and the other clocks, where one clock is sourced from the other.
657-
## Even though we describe the relationship, between this clocks in the design constraints.
658-
## Vivado tools(report_clock_interaction) cannot guarantee that the clocks are related.
659-
## We know the interactions between these clocks and can consider them safe so we will denote the CRITICAL WARNING.
660-
#set_msg_config -id {Timing 38-249} -string "Generated clock rx1_dclk_out has no logical paths from master clock ref_clk." -new_severity WARNING
661-
#set_msg_config -id {Timing 38-249} -string "Generated clock rx2_dclk_out has no logical paths from master clock ref_clk." -new_severity WARNING
662-
#set_msg_config -id {Timing 38-249} -string "Generated clock tx1_dclk_out has no logical paths from master clock ref_clk." -new_severity WARNING
663-
#set_msg_config -id {Timing 38-249} -string "Generated clock tx2_dclk_out has no logical paths from master clock ref_clk." -new_severity WARNING
664-
#set_msg_config -id {Timing 38-285} -string "Generated clock rx1_dclk_out has no logical paths from master clock fpga_ref_clk_p." -new_severity WARNING
665-
#set_msg_config -id {Timing 38-285} -string "Generated clock rx2_dclk_out has no logical paths from master clock fpga_ref_clk_p." -new_severity WARNING
666-
#set_msg_config -id {Timing 38-285} -string "Generated clock tx1_dclk_out has no logical paths from master clock fpga_ref_clk_p." -new_severity WARNING
667-
#set_msg_config -id {Timing 38-285} -string "Generated clock tx2_dclk_out has no logical paths from master clock fpga_ref_clk_p." -new_severity WARNING
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#

‎projects/jupiter_sdr/system_constr.xdc

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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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################################################################################
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‎projects/jupiter_sdr/system_project.tcl

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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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################################################################################
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‎projects/jupiter_sdr/system_top.v

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are

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