[BUG] Data on destination address zeroed after peripheral to memory DMA transaction with axi_dmac

[Vitorbnc]

Describe the bug
Using the axi_dmac in Vivado, I am able to transfer FIFO input data from peripheral to DDR only once using Autorun mode. But doing a software request to the same address sets the destination data to zero.

To Reproduce

1. Setup Vivado project with axi_dmac IP Block, set Source to FIFO width 32-bit, Destination to AXI3 64-bit wide, enable Autorun with Destination address 0x10000000. Connect fifo_wr_din[31:0] to a 32-bit constant block with 0xaabbccdd (test data), and fifo_wr_en to a single bit constant of 1.
2. Build a Vitis project with any of these sets of sources:

• no-os-driver-src.zip
• register-access-only-src.zip (uncomment line defining DMA_TEST_BUFFER1 to 0x10000000 if needed)

3. Connect to Zynq PS7 UART port with baud 115200 or add breakpoint on the last line of the while loop.
4. Start debug session to flash bitfile and program elf.
5. See that:

• Initial data on DMA_TEST_BUFFER1 (0x10000000) is the FIFO test data.
• Data is zeroed by memset at the start of the while loop.
• DMA transaction completes and interrupt is obtained, but data on DMA_TEST_BUFFER1 (0x10000000) is still zero.

Expected behavior
Data on destination (0x10000000) should be test data (0xaabbccdd) after each DMA transaction has been completed

Screenshots
Screenshot of the register-access-only version:

UART output (pyserial):

Desktop

• Project name: adaq23878_eval
• Carrier board: Omdazz XC7Z020 Zedboard-compatible with FMC
• Used Software: No-OS
• Tool version: Vivado 2020.2
• HDL Release version: git commit a22fce4
• No-OS Software Release version: git commit b75d62f

Additional context
Also, if I connect the DMA block to the ADC IP block, even after enabling Cyclic mode in the AXI_DMAC IP Block and setting the Autorun Flags to 0x1 (CYCLIC) or 0x7 (CYCLIC, TLAST,PARTIAL_REPORTING_EN), I only observe one DMA transfer. If I disable TESTPAT, I still see the same data on the destination buffer (0x330fc), it does not change if the ADC data changes (there is an ILA block and I can see that the ADC data is changing). Expected behavior is that the data on DDR destination would change as the ADC data changes.

Vivado block diagram with ADC block connected: design_1_adc_connected.pdf