diff --git a/docs/projects/adrv904x/adrv904x_block_diagram.svg b/docs/projects/adrv904x/adrv904x_block_diagram.svg index 8709c1810fc..ca2c3a685da 100644 --- a/docs/projects/adrv904x/adrv904x_block_diagram.svg +++ b/docs/projects/adrv904x/adrv904x_block_diagram.svg @@ -7,7 +7,7 @@ viewBox="0 0 1032.275 763.00399" id="svg5182" version="1.1" - inkscape:version="1.4.2 (f4327f4, 2025-05-13)" + inkscape:version="1.4.3 (0d15f75, 2025-12-25)" sodipodi:docname="adrv904x_block_diagram.svg" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" @@ -1126,7 +1126,11 @@ refX="0" id="TriangleOutM-1" style="overflow:visible" - inkscape:isstock="true"> + inkscape:isstock="true" + viewBox="0 0 4.25952648 4.92430807" + markerWidth="4.25952648" + markerHeight="4.92430807" + preserveAspectRatio="xMidYMid"> + inkscape:stockid="TriangleInL" + viewBox="0 0 8.51905296 9.84861614" + markerWidth="8.51905251" + markerHeight="9.84861561" + preserveAspectRatio="xMidYMid"> + + + + + + 512b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b + 512b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b link_clk rx_0 + y="1602.0793">rx_0 @250MHz + id="tspan102401">@300MHz rx_data_7_p, n + id="tspan2">rx_data_7_p, n ZCU102 rx_7rx_7 @250MHz + id="tspan102401-5">@300MHz core_clk BUF - - - - AXICLKGEN - - CLKGEN FCLK_CLK1 = 250MHz + id="tspan68-3">FCLK_CLK1 = 300MHz tx_out_clk_div2_0 rx_out_clk_div2_0 @@ -6228,5 +6240,20 @@ id="path6969-9-3" inkscape:connector-curvature="0" sodipodi:nodetypes="cc" /> + + + diff --git a/docs/projects/adrv904x/adrv904x_nls_block_diagram.svg b/docs/projects/adrv904x/adrv904x_nls_block_diagram.svg index 3a09ee4721e..de7767ad9fb 100644 --- a/docs/projects/adrv904x/adrv904x_nls_block_diagram.svg +++ b/docs/projects/adrv904x/adrv904x_nls_block_diagram.svg @@ -7,7 +7,7 @@ viewBox="0 0 1032.0863 1021.5216" id="svg5182" version="1.1" - inkscape:version="1.4.2 (f4327f4, 2025-05-13)" + inkscape:version="1.4.3 (0d15f75, 2025-12-25)" sodipodi:docname="adrv904x_nls_block_diagram.svg" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" @@ -3764,21 +3764,21 @@ inkscape:pageopacity="0.0" inkscape:pageshadow="2" inkscape:zoom="1.0000001" - inkscape:cx="300.49997" - inkscape:cy="467.99995" + inkscape:cx="515.99995" + inkscape:cy="691.49993" inkscape:document-units="px" inkscape:current-layer="layer1" showgrid="false" units="px" - inkscape:window-width="2400" - inkscape:window-height="1262" - inkscape:window-x="-8" - inkscape:window-y="-8" + inkscape:window-width="1920" + inkscape:window-height="991" + inkscape:window-x="-9" + inkscape:window-y="-9" inkscape:window-maximized="1" inkscape:pagecheckerboard="0" inkscape:showpageshadow="2" inkscape:deskcolor="#d1d1d1" - showguides="true" /> + showguides="false" /> @@ -4137,7 +4137,7 @@ id="tspan3345-9-10-7" x="80.591438" y="712.89606" - style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">512b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b 256b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b @250MHz + id="tspan102401">@300MHz @250MHz + id="tspan102401-5">@300MHz link_clk @250MHz + id="tspan26">@300MHz 256b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.217569">128b core_clk rx_7 128b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">256b BUF - - FCLK_CLK1 = 250MHz + id="tspan68-3">FCLK_CLK1 = 300MHz 32b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">16b 32b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">16b 32b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">16b 32b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">16b 8x2 16x1 + + + + diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index ea1752f337d..a5480188eef 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -192,8 +192,8 @@ Example block design for Single link and RX OBS in Non-LinkSharing mode The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 -- Sample Rate: 491.52 MSPS +- Rx Deframer parameters: L=4, M=16, F=8, S=1, NP=16, N=16 +- Sample Rate: 245.76 MSPS - Dual link: No - RX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) - REF_CLK: 491.52 MHz @@ -256,6 +256,7 @@ The following are the parameters of this project that can be configured: - [RX/TX/RX_OS]_JESD_L: number of lanes per link - [RX/TX/RX_OS]_JESD_S: number of samples per frame - [RX/TX/RX_OS]_JESD_NP: number of bits per sample +- [RX/TX/RX_OS]_TPL_WIDTH : TPL data path width in bits - [RX/TX/RX_OS]_NUM_LINKS: number of links Clock scheme @@ -459,18 +460,30 @@ for that project (adrv904x/carrier or adrv904x/carrier). +-------------------+------------------------------------------------------+ | RX_JESD_S | 1 | +-------------------+------------------------------------------------------+ + | RX_JESD_NP | 16 | + +-------------------+------------------------------------------------------+ + | RX_TPL_WIDTH | {} | + +-------------------+------------------------------------------------------+ | TX_JESD_M | 16 | +-------------------+------------------------------------------------------+ | TX_JESD_L | 8 | +-------------------+------------------------------------------------------+ | TX_JESD_S | 1 | +-------------------+------------------------------------------------------+ + | TX_JESD_NP | 16 | + +-------------------+------------------------------------------------------+ + | TX_TPL_WIDTH | {} | + +-------------------+------------------------------------------------------+ | RX_OS_JESD_M | 0 | +-------------------+------------------------------------------------------+ | RX_OS_JESD_L | 0 | +-------------------+------------------------------------------------------+ | RX_OS_JESD_S | 0 | +-------------------+------------------------------------------------------+ + | RX_OS_JESD_NP | 0 | + +-------------------+------------------------------------------------------+ + | RX_OS_TPL_WIDTH | {} | + +-------------------+------------------------------------------------------+ A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -484,18 +497,18 @@ ADC - lane mapping Due to physical constraints, Rx lanes are reordered as described in the following table. -============ =========================== -ADC phy Lane FPGA Rx lane / Logical Lane -============ =========================== -0 0 -1 1 -2 2 -3 3 -4 4 -5 5 -6 6 -7 7 -============ =========================== +======== =========== ====== ============== ============= ========== +ADC Lane GTH Channel FMC DP FPGA Rx lane XCVR Lane Link layer +======== =========== ====== ============== ============= ========== +SERDOUT0 MGTHRX1_228 DP5 rx_data_p/n[0] rx_data_1_p/n rx_phy5 +SERDOUT1 MGTHRX0_228 DP6 rx_data_p/n[1] rx_data_2_p/n rx_phy6 +SERDOUT2 MGTHRX3_228 DP4 rx_data_p/n[2] rx_data_0_p/n rx_phy4 +SERDOUT3 MGTHRX2_228 DP7 rx_data_p/n[3] rx_data_3_p/n rx_phy7 +SERDOUT4 MGTHRX3_229 DP2 rx_data_p/n[4] rx_data_5_p/n rx_phy2 +SERDOUT5 MGTHRX0_229 DP3 rx_data_p/n[5] rx_data_4_p/n rx_phy3 +SERDOUT6 MGTHRX1_229 DP1 rx_data_p/n[6] rx_data_6_p/n rx_phy1 +SERDOUT7 MGTHRX2_229 DP0 rx_data_p/n[7] rx_data_7_p/n rx_phy0 +======== =========== ====== ============== ============= ========== DAC - lane mapping ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -503,18 +516,18 @@ DAC - lane mapping Due to physical constraints, Tx lanes are reordered as described in the following table. -============ =========================== -DAC phy lane FPGA Tx lane / Logical lane -============ =========================== -0 7 -1 6 -2 4 -3 5 -4 3 -5 1 -6 0 -7 2 -============ =========================== +======== =========== ====== ============== ============= ========== +DAC Lane GTH Channel FMC DP FPGA Tx lane XCVR Lane Link layer +======== =========== ====== ============== ============= ========== +SERDIN0 MGTHTX2_229 DP0 tx_data_p/n[0] tx_data_7_p/n tx_phy0 +SERDIN1 MGTHTX1_229 DP1 tx_data_p/n[1] tx_data_6_p/n tx_phy1 +SERDIN2 MGTHTX3_229 DP2 tx_data_p/n[2] tx_data_5_p/n tx_phy2 +SERDIN3 MGTHTX0_229 DP3 tx_data_p/n[3] tx_data_4_p/n tx_phy3 +SERDIN4 MGTHTX2_228 DP7 tx_data_p/n[4] tx_data_0_p/n tx_phy4 +SERDIN5 MGTHTX0_228 DP6 tx_data_p/n[5] tx_data_1_p/n tx_phy5 +SERDIN6 MGTHTX1_228 DP5 tx_data_p/n[6] tx_data_2_p/n tx_phy6 +SERDIN7 MGTHTX3_228 DP4 tx_data_p/n[7] tx_data_3_p/n tx_phy7 +======== =========== ====== ============== ============= ========== Resources ------------------------------------------------------------------------------- diff --git a/projects/adrv904x/common/adrv904x_bd.tcl b/projects/adrv904x/common/adrv904x_bd.tcl index 6c724aabcc3..8a3886b710f 100644 --- a/projects/adrv904x/common/adrv904x_bd.tcl +++ b/projects/adrv904x/common/adrv904x_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -38,6 +38,13 @@ if {$JESD_MODE == "8B10B"} { set ENCODER_SEL 2 } +set TX_TPL_WIDTH [ expr { [info exists ad_project_params(TX_TPL_WIDTH)] \ + ? $ad_project_params(TX_TPL_WIDTH) : {} } ] +set RX_TPL_WIDTH [ expr { [info exists ad_project_params(RX_TPL_WIDTH)] \ + ? $ad_project_params(RX_TPL_WIDTH) : {} } ] +set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \ + ? $ad_project_params(RX_OS_TPL_WIDTH) : {} } ] + source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl @@ -52,7 +59,7 @@ if {$TX_DMA_SAMPLE_WIDTH == 12} { set TX_DMA_SAMPLE_WIDTH 16 } -set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX_JESD_M $TX_JESD_S $TX_JESD_NP] +set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_NUM_OF_LANES $TX_NUM_OF_CONVERTERS $TX_SAMPLES_PER_FRAME $TX_SAMPLE_WIDTH $TX_TPL_WIDTH] set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] # RX parameters @@ -66,7 +73,7 @@ if {$RX_DMA_SAMPLE_WIDTH == 12} { set RX_DMA_SAMPLE_WIDTH 16 } -set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_JESD_L $RX_JESD_M $RX_JESD_S $RX_JESD_NP] +set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_NUM_OF_LANES $RX_NUM_OF_CONVERTERS $RX_SAMPLES_PER_FRAME $RX_SAMPLE_WIDTH $RX_TPL_WIDTH] set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8* $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] set adc_data_offload_name adrv904x_rx_data_offload @@ -93,11 +100,13 @@ if {$RX_OS_DMA_SAMPLE_WIDTH == 12} { } if {$ORX_ENABLE} { - set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_JESD_L $RX_OS_JESD_M $RX_OS_JESD_S $RX_OS_JESD_NP] + set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH $RX_OS_TPL_WIDTH] set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8* $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] } -set MAX_RX_NUM_OF_LANES [expr $ORX_ENABLE ? [expr $RX_NUM_OF_LANES + $RX_OS_NUM_OF_LANES] : $RX_NUM_OF_LANES] +set MAX_RX_NUM_OF_LANES [expr $ORX_ENABLE ? 4 : 8] +set MAX_TX_NUM_OF_LANES 8 +set MAX_RX_OS_NUM_OF_LANES [expr $ORX_ENABLE ? 4 : 0] # adrv904x @@ -115,7 +124,7 @@ ad_ip_parameter axi_adrv904x_tx_clkgen CONFIG.CLK0_DIV 4 ad_ip_instance axi_adxcvr axi_adrv904x_tx_xcvr ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES +ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.TX_OR_RX_N 1 ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.SYS_CLK_SEL 3 @@ -173,7 +182,7 @@ ad_ip_parameter axi_adrv904x_rx_clkgen CONFIG.CLK0_DIV 4 ad_ip_instance axi_adxcvr axi_adrv904x_rx_xcvr ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES +ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.SYS_CLK_SEL 3 @@ -230,7 +239,7 @@ if {$ORX_ENABLE} { ad_ip_instance axi_adxcvr axi_adrv904x_rx_os_xcvr ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.LINK_MODE $ENCODER_SEL - ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.NUM_OF_LANES $RX_OS_NUM_OF_LANES + ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_adrv904x_rx_os_xcvr CONFIG.SYS_CLK_SEL 0 @@ -279,8 +288,8 @@ create_bd_port -dir I $rx_obs_ref_clk # common cores ad_ip_instance util_adxcvr util_adrv904x_xcvr -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES +ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES + $MAX_RX_OS_NUM_OF_LANES] +ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES ad_ip_parameter util_adrv904x_xcvr CONFIG.LINK_MODE $ENCODER_SEL ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE @@ -336,11 +345,7 @@ ad_connect $sys_cpu_clk util_adrv904x_xcvr/up_clk ad_connect adrv904x_tx_device_clk axi_adrv904x_tx_clkgen/clk_0 ad_connect core_clk axi_adrv904x_tx_clkgen/clk -if {$ORX_ENABLE} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_tx_xcvr axi_adrv904x_tx_jesd {7 6 4 5 3 1 0 2} {} adrv904x_tx_device_clk $TX_NUM_OF_LANES {} -} else { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_tx_xcvr axi_adrv904x_tx_jesd {7 6 4 5 2 0 1 3} {} adrv904x_tx_device_clk $TX_NUM_OF_LANES {} -} +ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_tx_xcvr axi_adrv904x_tx_jesd {} {} adrv904x_tx_device_clk $MAX_TX_NUM_OF_LANES {7 6 5 4 3 2 1 0} ad_xcvrpll $tx_ref_clk util_adrv904x_xcvr/qpll_ref_clk_0 ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_0 @@ -351,21 +356,9 @@ ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_4 ad_connect adrv904x_rx_device_clk axi_adrv904x_rx_clkgen/clk_0 ad_connect core_clk axi_adrv904x_rx_clkgen/clk -if {$RX_NUM_OF_LANES == 8} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} adrv904x_rx_device_clk $RX_NUM_OF_LANES {7 6 4 5 2 0 1 3} -} else { - if {$RX_NUM_OF_LANES == 4} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} adrv904x_rx_device_clk $RX_NUM_OF_LANES {} - } else { - if {$RX_NUM_OF_LANES == 2} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} adrv904x_rx_device_clk $RX_NUM_OF_LANES {} - } else { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} adrv904x_rx_device_clk $RX_NUM_OF_LANES {} - } - } -} +ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} adrv904x_rx_device_clk $MAX_RX_NUM_OF_LANES {1 2 0 3 5 4 6 7} -for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { +for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} { if {$i < 4} { ad_xcvrpll $rx_ref_clk util_adrv904x_xcvr/cpll_ref_clk_$i ad_xcvrpll axi_adrv904x_rx_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$i @@ -380,44 +373,20 @@ if {$ORX_ENABLE} { ad_connect adrv904x_rx_os_device_clk axi_adrv904x_rx_os_clkgen/clk_0 ad_connect core_clk axi_adrv904x_rx_os_clkgen/clk - if {$RX_OS_NUM_OF_LANES == 4} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_os_xcvr axi_adrv904x_rx_os_jesd {} {} adrv904x_rx_os_device_clk $RX_OS_NUM_OF_LANES {4 5 6 7} - } else { - if {$RX_OS_NUM_OF_LANES == 2} { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_os_xcvr axi_adrv904x_rx_os_jesd {} {} adrv904x_rx_os_device_clk $RX_OS_NUM_OF_LANES {4 5} - } else { - ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_os_xcvr axi_adrv904x_rx_os_jesd {} {} adrv904x_rx_os_device_clk $RX_OS_NUM_OF_LANES {4} - } - } + ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_os_xcvr axi_adrv904x_rx_os_jesd {4 5 6 7} {} adrv904x_rx_os_device_clk $MAX_RX_OS_NUM_OF_LANES {5 4 6 7} - for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} { - set ch [expr $RX_NUM_OF_LANES + $i] + for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} { + set ch [expr $MAX_RX_NUM_OF_LANES + $i] ad_xcvrpll $rx_obs_ref_clk util_adrv904x_xcvr/cpll_ref_clk_$ch ad_xcvrpll axi_adrv904x_rx_os_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$ch } - if {$MAX_RX_NUM_OF_LANES < $TX_NUM_OF_LANES} { - for {set i $MAX_RX_NUM_OF_LANES} {$i < $TX_NUM_OF_LANES} {incr i} { - ad_xcvrpll $rx_obs_ref_clk util_adrv904x_xcvr/cpll_ref_clk_$i - } - } - delete_bd_objs [get_bd_ports rx_sync_$RX_NUM_OF_LANES] - delete_bd_objs [get_bd_ports rx_sysref_$RX_NUM_OF_LANES] + + delete_bd_objs [get_bd_ports rx_sync_$MAX_RX_NUM_OF_LANES] + delete_bd_objs [get_bd_ports rx_sysref_$MAX_RX_NUM_OF_LANES] ad_connect rx_os_sync axi_adrv904x_rx_os_jesd_sync ad_connect rx_os_sysref sysref_3 } -# Unused Rx lanes -for {set i $MAX_RX_NUM_OF_LANES} {$i < 8} {incr i} { - create_bd_port -dir I rx_data_${i}_n - create_bd_port -dir I rx_data_${i}_p -} - -# Unused Tx lanes -for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { - create_bd_port -dir O tx_data_${i}_n - create_bd_port -dir O tx_data_${i}_p -} - # connections (dac) ad_connect adrv904x_tx_device_clk tx_adrv904x_tpl_core/link_clk diff --git a/projects/adrv904x/common/adrv904x_fmc.txt b/projects/adrv904x/common/adrv904x_fmc.txt index 1ce9d1fa95f..e5b90f96090 100755 --- a/projects/adrv904x/common/adrv904x_fmc.txt +++ b/projects/adrv904x/common/adrv904x_fmc.txt @@ -31,22 +31,22 @@ A3 DP1_M2C_N SERDOUT6+ rx_data_n[6] #N/A #N/A C6 DP0_M2C_P SERDOUT7- rx_data_p[7] #N/A #N/A C7 DP0_M2C_N SERDOUT7+ rx_data_n[7] #N/A #N/A -A38 DP5_C2M_P SERDIN6+ tx_data_p[0] #N/A #N/A -A39 DP5_C2M_N SERDIN6- tx_data_n[0] #N/A #N/A -B36 DP6_C2M_P SERDIN5+ tx_data_p[1] #N/A #N/A -B37 DP6_C2M_N SERDIN5- tx_data_n[1] #N/A #N/A -A34 DP4_C2M_P SERDIN7+ tx_data_p[2] #N/A #N/A -A35 DP4_C2M_N SERDIN7- tx_data_n[2] #N/A #N/A -B32 DP7_C2M_P SERDIN4+ tx_data_p[3] #N/A #N/A -B33 DP7_C2M_N SERDIN4- tx_data_n[3] #N/A #N/A -A26 DP2_C2M_P SERDIN2- tx_data_p[4] #N/A #N/A -A27 DP2_C2M_N SERDIN2+ tx_data_n[4] #N/A #N/A -A30 DP3_C2M_P SERDIN3- tx_data_p[5] #N/A #N/A -A31 DP3_C2M_N SERDIN3+ tx_data_n[5] #N/A #N/A -A22 DP1_C2M_P SERDIN1- tx_data_p[6] #N/A #N/A -A23 DP1_C2M_N SERDIN1+ tx_data_n[6] #N/A #N/A -C2 DP0_C2M_P SERDIN0- tx_data_p[7] #N/A #N/A -C3 DP0_C2M_N SERDIN0+ tx_data_n[7] #N/A #N/A +C2 DP0_C2M_P SERDIN0- tx_data_p[0] #N/A #N/A +C3 DP0_C2M_N SERDIN0+ tx_data_n[0] #N/A #N/A +A22 DP1_C2M_P SERDIN1- tx_data_p[1] #N/A #N/A +A23 DP1_C2M_N SERDIN1+ tx_data_n[1] #N/A #N/A +A26 DP2_C2M_P SERDIN2- tx_data_p[2] #N/A #N/A +A27 DP2_C2M_N SERDIN2+ tx_data_n[2] #N/A #N/A +A30 DP3_C2M_P SERDIN3- tx_data_p[3] #N/A #N/A +A31 DP3_C2M_N SERDIN3+ tx_data_n[3] #N/A #N/A +B32 DP7_C2M_P SERDIN4+ tx_data_p[4] #N/A #N/A +B33 DP7_C2M_N SERDIN4- tx_data_n[4] #N/A #N/A +B36 DP6_C2M_P SERDIN5+ tx_data_p[5] #N/A #N/A +B37 DP6_C2M_N SERDIN5- tx_data_n[5] #N/A #N/A +A38 DP5_C2M_P SERDIN6+ tx_data_p[6] #N/A #N/A +A39 DP5_C2M_N SERDIN6- tx_data_n[6] #N/A #N/A +A34 DP4_C2M_P SERDIN7+ tx_data_p[7] #N/A #N/A +A35 DP4_C2M_N SERDIN7- tx_data_n[7] #N/A #N/A H7 LA02_P SYNCOUT0+ rx_sync_p LVDS #N/A H8 LA02_N SYNCOUT0- rx_sync_n LVDS #N/A @@ -132,4 +132,4 @@ D14 LA09_P SPI_CS0 spi_csn_adrv904x LVCMOS18 #N/A D15 LA09_N SPI_CS1 spi_csn_ad9528 LVCMOS18 #N/A H13 LA07_P SPI_CLK spi_clk LVCMOS18 #N/A G12 LA08_P SPI_DOUT spi_miso LVCMOS18 #N/A -H14 LA07_N SPI_DIN spi_mosi LVCMOS18 #N/A \ No newline at end of file +H14 LA07_N SPI_DIN spi_mosi LVCMOS18 #N/A diff --git a/projects/adrv904x/zcu102/README.md b/projects/adrv904x/zcu102/README.md index b2d5575e483..8428401e6e2 100644 --- a/projects/adrv904x/zcu102/README.md +++ b/projects/adrv904x/zcu102/README.md @@ -32,6 +32,7 @@ The overwritable parameters from the environment: - [RX/TX/RX_OS]_JESD_L - [RX/TX/RX_OS] number of lanes per link - [RX/TX/RX_OS]_JESD_S - [RX/TX/RX_OS] number of samples per converter per frame - [RX/TX/RX_OS]_JESD_NP - [RX/TX/RX_OS] number of bits per sample, only 16 is supported +- [RX/TX/RX_OS]_TPL_WIDTH - [RX/TX/RX_OS] TPL data path width in bits - [RX/TX/RX_OS]_NUM_LINKS - [RX/TX/RX_OS] number of links ### Example configurations @@ -52,14 +53,17 @@ RX_JESD_M=16 \ RX_JESD_L=8 \ RX_JESD_S=1 \ RX_JESD_NP=16 \ +RX_TPL_WIDTH={} \ TX_JESD_M=16 \ TX_JESD_L=8 \ TX_JESD_S=1 \ TX_JESD_NP=16 \ +TX_TPL_WIDTH={} \ RX_OS_JESD_M=0 \ RX_OS_JESD_L=0 \ RX_OS_JESD_S=0 \ -RX_OS_JESD_NP=0 +RX_OS_JESD_NP=0 \ +RX_OS_TPL_WIDTH={} ``` Corresponding device tree: [zynqmp-zcu102-rev10-adrv904x.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv904x.dts) @@ -74,18 +78,21 @@ TX_LANE_RATE=16.22 \ RX_NUM_LINKS=1 \ TX_NUM_LINK=1 \ RX_OS_NUM_LINKS=1 \ -RX_JESD_M=8 \ +RX_JESD_M=16 \ RX_JESD_L=4 \ RX_JESD_S=1 \ RX_JESD_NP=16 \ +RX_TPL_WIDTH={} \ TX_JESD_M=16 \ TX_JESD_L=8 \ TX_JESD_S=1 \ TX_JESD_NP=16 \ +TX_TPL_WIDTH={} \ RX_OS_JESD_M=8 \ RX_OS_JESD_L=4 \ RX_OS_JESD_S=1 \ -RX_OS_JESD_NP=16 +RX_OS_JESD_NP=16 \ +RX_OS_TPL_WIDTH={} ``` -Corresponding device tree: [zynqmp-zcu102-rev10-adrv904x-nls.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv904x-nls.dts) \ No newline at end of file +Corresponding device tree: [zynqmp-zcu102-rev10-adrv904x-nls.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv904x-nls.dts) diff --git a/projects/adrv904x/zcu102/system_bd.tcl b/projects/adrv904x/zcu102/system_bd.tcl index 8adf53bbb71..70d2e627d2d 100644 --- a/projects/adrv904x/zcu102/system_bd.tcl +++ b/projects/adrv904x/zcu102/system_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -42,3 +42,5 @@ LINKS=$ad_project_params(RX_OS_NUM_LINKS)" sysid_gen_sys_init_file source ../common/adrv904x_bd.tcl + +ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {300} diff --git a/projects/adrv904x/zcu102/system_constr.xdc b/projects/adrv904x/zcu102/system_constr.xdc index a75d0c9831b..20fb3bae07c 100644 --- a/projects/adrv904x/zcu102/system_constr.xdc +++ b/projects/adrv904x/zcu102/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -30,22 +30,22 @@ set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[6]] set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[7]] ; ## C6 FMC0_DP0_M2C_P MGTHRXP2_229 (rx_data_n[7]) set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[7]] ; ## C7 FMC0_DP0_M2C_N MGTHRXN2_229 (rx_data_p[7]) -set_property -dict {PACKAGE_PIN P6} [get_ports tx_data_p[0]] ; ## A38 FMC0_DP5_C2M_P MGTHTXP1_228 (tx_data_n[6]) -set_property -dict {PACKAGE_PIN P5} [get_ports tx_data_n[0]] ; ## A39 FMC0_DP5_C2M_N MGTHTXN1_228 (tx_data_p[6]) -set_property -dict {PACKAGE_PIN R4} [get_ports tx_data_p[1]] ; ## B36 FMC0_DP6_C2M_P MGTHTXP0_228 (tx_data_n[5]) -set_property -dict {PACKAGE_PIN R3} [get_ports tx_data_n[1]] ; ## B37 FMC0_DP6_C2M_N MGTHTXN0_228 (tx_data_p[5]) -set_property -dict {PACKAGE_PIN M6} [get_ports tx_data_p[2]] ; ## A34 FMC0_DP4_C2M_P MGTHTXP3_228 (tx_data_n[7]) -set_property -dict {PACKAGE_PIN M5} [get_ports tx_data_n[2]] ; ## A35 FMC0_DP4_C2M_N MGTHTXN3_228 (tx_data_p[7]) -set_property -dict {PACKAGE_PIN N4} [get_ports tx_data_p[3]] ; ## B32 FMC0_DP7_C2M_P MGTHTXP2_228 (tx_data_n[4]) -set_property -dict {PACKAGE_PIN N3} [get_ports tx_data_n[3]] ; ## B33 FMC0_DP7_C2M_N MGTHTXN2_228 (tx_data_p[4]) -set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[4]] ; ## A26 FMC0_DP2_C2M_P MGTHTXP3_229 (tx_data_n[2]) -set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[4]] ; ## A27 FMC0_DP2_C2M_N MGTHTXN3_229 (tx_data_p[2]) -set_property -dict {PACKAGE_PIN K6} [get_ports tx_data_p[5]] ; ## A30 FMC0_DP3_C2M_P MGTHTXP0_229 (tx_data_n[3]) -set_property -dict {PACKAGE_PIN K5} [get_ports tx_data_n[5]] ; ## A31 FMC0_DP3_C2M_N MGTHTXN0_229 (tx_data_p[3]) -set_property -dict {PACKAGE_PIN H6} [get_ports tx_data_p[6]] ; ## A22 FMC0_DP1_C2M_P MGTHTXP1_229 (tx_data_n[1]) -set_property -dict {PACKAGE_PIN H5} [get_ports tx_data_n[6]] ; ## A23 FMC0_DP1_C2M_N MGTHTXN1_229 (tx_data_p[1]) -set_property -dict {PACKAGE_PIN G4} [get_ports tx_data_p[7]] ; ## C2 FMC0_DP0_C2M_P MGTHTXP2_229 (tx_data_n[0]) -set_property -dict {PACKAGE_PIN G3} [get_ports tx_data_n[7]] ; ## C3 FMC0_DP0_C2M_N MGTHTXN2_229 (tx_data_p[0]) +set_property -dict {PACKAGE_PIN G4} [get_ports tx_data_p[0]] ; ## C2 FMC0_DP0_C2M_P MGTHTXP2_229 (tx_data_n[0]) +set_property -dict {PACKAGE_PIN G3} [get_ports tx_data_n[0]] ; ## C3 FMC0_DP0_C2M_N MGTHTXN2_229 (tx_data_p[0]) +set_property -dict {PACKAGE_PIN H6} [get_ports tx_data_p[1]] ; ## A22 FMC0_DP1_C2M_P MGTHTXP1_229 (tx_data_n[1]) +set_property -dict {PACKAGE_PIN H5} [get_ports tx_data_n[1]] ; ## A23 FMC0_DP1_C2M_N MGTHTXN1_229 (tx_data_p[1]) +set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[2]] ; ## A26 FMC0_DP2_C2M_P MGTHTXP3_229 (tx_data_n[2]) +set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[2]] ; ## A27 FMC0_DP2_C2M_N MGTHTXN3_229 (tx_data_p[2]) +set_property -dict {PACKAGE_PIN K6} [get_ports tx_data_p[3]] ; ## A30 FMC0_DP3_C2M_P MGTHTXP0_229 (tx_data_n[3]) +set_property -dict {PACKAGE_PIN K5} [get_ports tx_data_n[3]] ; ## A31 FMC0_DP3_C2M_N MGTHTXN0_229 (tx_data_p[3]) +set_property -dict {PACKAGE_PIN N4} [get_ports tx_data_p[4]] ; ## B32 FMC0_DP7_C2M_P MGTHTXP2_228 (tx_data_n[4]) +set_property -dict {PACKAGE_PIN N3} [get_ports tx_data_n[4]] ; ## B33 FMC0_DP7_C2M_N MGTHTXN2_228 (tx_data_p[4]) +set_property -dict {PACKAGE_PIN R4} [get_ports tx_data_p[5]] ; ## B36 FMC0_DP6_C2M_P MGTHTXP0_228 (tx_data_n[5]) +set_property -dict {PACKAGE_PIN R3} [get_ports tx_data_n[5]] ; ## B37 FMC0_DP6_C2M_N MGTHTXN0_228 (tx_data_p[5]) +set_property -dict {PACKAGE_PIN P6} [get_ports tx_data_p[6]] ; ## A38 FMC0_DP5_C2M_P MGTHTXP1_228 (tx_data_n[6]) +set_property -dict {PACKAGE_PIN P5} [get_ports tx_data_n[6]] ; ## A39 FMC0_DP5_C2M_N MGTHTXN1_228 (tx_data_p[6]) +set_property -dict {PACKAGE_PIN M6} [get_ports tx_data_p[7]] ; ## A34 FMC0_DP4_C2M_P MGTHTXP3_228 (tx_data_n[7]) +set_property -dict {PACKAGE_PIN M5} [get_ports tx_data_n[7]] ; ## A35 FMC0_DP4_C2M_N MGTHTXN3_228 (tx_data_p[7]) set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H7 FMC0_LA02_P IO_L23P_T3U_N8_66 set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H8 FMC0_LA02_N IO_L23N_T3U_N9_66 diff --git a/projects/adrv904x/zcu102/system_project.tcl b/projects/adrv904x/zcu102/system_project.tcl index 7ab11fe6cda..1d3d0889cc4 100644 --- a/projects/adrv904x/zcu102/system_project.tcl +++ b/projects/adrv904x/zcu102/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -14,7 +14,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # # e.g. # RX-OS disabled: make -# RX-OS Non-LinkSharing: make ORX_ENABLE=1 LINK_SHARING=0 RX_OS_JESD_M=8 RX_OS_JESD_L=4 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_M=8 RX_JESD_L=4 +# RX-OS Non-LinkSharing: make ORX_ENABLE=1 RX_OS_JESD_M=8 RX_OS_JESD_L=4 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_L=4 # # Parameter description: # JESD_MODE : Used link layer encoder mode @@ -30,6 +30,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # [TX/RX/RX_OS]_JESD_L : Number of lanes per link # [TX/RX/RX_OS]_JESD_S : Number of samples per frame # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +# [TX/RX/RX_OS]_TPL_WIDTH : TPL data path width in bits adi_project adrv904x_zcu102 0 [list \ JESD_MODE [get_env_param JESD_MODE 64B66B] \ @@ -43,14 +44,17 @@ adi_project adrv904x_zcu102 0 [list \ TX_JESD_L [get_env_param TX_JESD_L 8] \ TX_JESD_S [get_env_param TX_JESD_S 1] \ TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {}] \ RX_JESD_M [get_env_param RX_JESD_M 16] \ RX_JESD_L [get_env_param RX_JESD_L 8] \ RX_JESD_S [get_env_param RX_JESD_S 1] \ RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {}] \ RX_OS_JESD_M [get_env_param RX_OS_JESD_M 0] \ RX_OS_JESD_L [get_env_param RX_OS_JESD_L 0] \ RX_OS_JESD_S [get_env_param RX_OS_JESD_S 0] \ RX_OS_JESD_NP [get_env_param RX_OS_JESD_NP 0] \ + RX_OS_TPL_WIDTH [get_env_param RX_OS_TPL_WIDTH {}] \ ] adi_project_files adrv904x_zcu102 [list \ diff --git a/projects/adrv904x/zcu102/system_top.v b/projects/adrv904x/zcu102/system_top.v index fbf867c2a93..d1b4e0fc194 100644 --- a/projects/adrv904x/zcu102/system_top.v +++ b/projects/adrv904x/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -201,18 +201,18 @@ module system_top ( .gpio_o (gpio_o), .gpio_t (gpio_t), .core_clk(core_clk_buf), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_data_2_n (rx_data_n[2]), - .rx_data_2_p (rx_data_p[2]), + .rx_data_0_n (rx_data_n[2]), + .rx_data_0_p (rx_data_p[2]), + .rx_data_1_n (rx_data_n[0]), + .rx_data_1_p (rx_data_p[0]), + .rx_data_2_n (rx_data_n[1]), + .rx_data_2_p (rx_data_p[1]), .rx_data_3_n (rx_data_n[3]), .rx_data_3_p (rx_data_p[3]), - .rx_data_4_n (rx_data_n[4]), - .rx_data_4_p (rx_data_p[4]), - .rx_data_5_n (rx_data_n[5]), - .rx_data_5_p (rx_data_p[5]), + .rx_data_4_n (rx_data_n[5]), + .rx_data_4_p (rx_data_p[5]), + .rx_data_5_n (rx_data_n[4]), + .rx_data_5_p (rx_data_p[4]), .rx_data_6_n (rx_data_n[6]), .rx_data_6_p (rx_data_p[6]), .rx_data_7_n (rx_data_n[7]), @@ -232,22 +232,22 @@ module system_top ( .spi1_csn (), .spi1_miso (1'b0), .spi1_mosi (), - .tx_data_0_n (tx_data_n[0]), - .tx_data_0_p (tx_data_p[0]), - .tx_data_1_n (tx_data_n[1]), - .tx_data_1_p (tx_data_p[1]), - .tx_data_2_n (tx_data_n[2]), - .tx_data_2_p (tx_data_p[2]), - .tx_data_3_n (tx_data_n[3]), - .tx_data_3_p (tx_data_p[3]), - .tx_data_4_n (tx_data_n[4]), - .tx_data_4_p (tx_data_p[4]), - .tx_data_5_n (tx_data_n[5]), - .tx_data_5_p (tx_data_p[5]), - .tx_data_6_n (tx_data_n[6]), - .tx_data_6_p (tx_data_p[6]), - .tx_data_7_n (tx_data_n[7]), - .tx_data_7_p (tx_data_p[7]), + .tx_data_0_n (tx_data_n[7]), + .tx_data_0_p (tx_data_p[7]), + .tx_data_1_n (tx_data_n[6]), + .tx_data_1_p (tx_data_p[6]), + .tx_data_2_n (tx_data_n[5]), + .tx_data_2_p (tx_data_p[5]), + .tx_data_3_n (tx_data_n[4]), + .tx_data_3_p (tx_data_p[4]), + .tx_data_4_n (tx_data_n[0]), + .tx_data_4_p (tx_data_p[0]), + .tx_data_5_n (tx_data_n[1]), + .tx_data_5_p (tx_data_p[1]), + .tx_data_6_n (tx_data_n[2]), + .tx_data_6_p (tx_data_p[2]), + .tx_data_7_n (tx_data_n[3]), + .tx_data_7_p (tx_data_p[3]), .tx_ref_clk_0 (ref_clk0), .tx_ref_clk_1 (ref_clk0), .tx_sync_0 (tx_sync),