fix(test): apply AD9081 rx/tx JESD modes per side in system-hw test

AD9081 uses different jesd204b link modes for its ADC (RX, jtx) and
DAC (TX, jrx) paths — the per-side MODE_TABLE in
adidt.devices.converters.ad9081 maps `(10, "jesd204b")` → L=4 for
RX and `(9, "jesd204b")` → L=4 for TX, with no entry for the
opposite side.

The System-hw test called
`fmc.converter.set_jesd204_mode(cfg["rx_mode"], cfg["rx_class"])`,
which applies rx_mode=10 to *both* sides.  The DAC's MODE_TABLE
lookup then missed, its framing parameters stayed at defaults (L=0),
and the kernel driver aborted at
`adi_ad9081_device_startup_tx_or_nco_test` with
`jesd_param->jesd_l == 0` → `Failed to initialize: -14`.

Set each side with its own solver-derived mode:

    fmc.converter.adc.set_jesd204_mode(cfg["rx_mode"], cfg["rx_class"])
    fmc.converter.dac.set_jesd204_mode(cfg["tx_mode"], cfg["tx_class"])

`cfg["tx_mode"]` was already being populated by `_solve_ad9081_config`;
it was just being discarded at the apply step.

Author: tfcollins

test/hw/test_ad9081_zcu102_system_hw.py

@@ -116,8 +116,18 @@ def _solve_ad9081_config(vcxo_hz: int = DEFAULT_VCXO_HZ) -> dict:
 
 
 def _configure_converter(fmc, cfg: dict) -> None:
-    """Apply solver-resolved JESD + datapath values to the AD9081 device."""
-    fmc.converter.set_jesd204_mode(cfg["rx_mode"], cfg["rx_class"])
+    """Apply solver-resolved JESD + datapath values to the AD9081 device.
+
+    AD9081 uses *different* jesd204b link modes for the ADC (RX, jtx)
+    and DAC (TX, jrx) sides — see the per-side ``MODE_TABLE`` in
+    :mod:`adidt.devices.converters.ad9081`.  Applying the same mode to
+    both sides via ``converter.set_jesd204_mode`` leaves the DAC
+    mode-table lookup empty and L=0, which makes the kernel driver
+    fail at ``adi_ad9081_device_startup_tx_or_nco_test`` with
+    ``jesd_param->jesd_l == 0``.  Set each side individually instead.
+    """
+    fmc.converter.adc.set_jesd204_mode(cfg["rx_mode"], cfg["rx_class"])
+    fmc.converter.dac.set_jesd204_mode(cfg["tx_mode"], cfg["tx_class"])
     fmc.converter.adc.sample_rate = cfg["rx_sample_rate"]
     fmc.converter.dac.sample_rate = cfg["tx_sample_rate"]
     fmc.converter.adc.cddc_decimation = cfg["rx_cddc"]