fix(adrv937x): wire clkgen clkin1 to AD9528 ch1 to fix clock-rate mismatch

Diagnostic output from the JESD-status assert added in e4065c1
showed the real cause of the DMA timeout:

    === JESD204 RX status (sysfs) ===
    Link is disabled
    Measured Link Clock: 122.882 MHz
    Reported Link Clock: 245.760 MHz
    ...

2× mismatch between measured and reported — the DT was telling the
driver ``clkin1 = 245.76 MHz`` (via the ``misc_clk_0`` fixed-clock
overlay) while the physical clock routed into the clkgen from the
AD9528 FMC output is actually 122.88 MHz.  The driver couldn't
resolve the mismatch so it marked the link disabled, which stalls
the TPL DMA even though the Mykonos-side jesd204 FSM reaches
``opt_post_running_stage``.

Minimum targeted fix: swap the clkgen's ``clkin1`` reference
from ``misc_clk_0`` to ``<&clk0_ad9528 1>`` (the same wiring the
Kuiper reference DT uses) and drop the now-unused
``misc_clk_0`` overlay.  Adxcvr is untouched — still routes
through the clkgen for both conv + div40.  This is a clocks-only
change, no behavioural change on any other property, so it
avoids the kernel-hang class the full rewire (commit 607663b)
triggered.

Unit tests: 449 passed, 13 skipped, 4 xfailed.  Hw CI will tell
us on the next bq leg whether "Link status: DATA" comes back and
the DMA starts streaming.

Author: tfcollins

adidt/xsa/builders/adrv937x.py

@@ -523,34 +523,46 @@ def build_model(
         )
 
         # --- Clkgen overlay nodes ---
+        # Point ``clkin1`` at AD9528 channel 1 (FMC_CLK) to match the
+        # physical clock routing.  The previous overlay left
+        # ``clkin1`` bound to the sdtgen-inherited ``misc_clk_0``
+        # fixed-clock (which we were setting to 245.76 MHz), but the
+        # physical FMC clock from AD9528 is 122.88 MHz.  The
+        # axi-jesd204-rx sysfs status directly showed the
+        # consequence: ``Measured Link Clock: 122.882 MHz`` +
+        # ``Reported Link Clock: 245.760 MHz`` → "Link is disabled"
+        # → TPL DMA never sees valid samples.  Ref DT on bq uses
+        # the same AD9528-ch1 clkin1 wiring.  ``clocks`` with
+        # explicit ``/delete-property/`` of the inherited xlnx
+        # clocks list forces the overlay's value to win.
+        clkgen_clocks = (
+            f"<&{ps_clk_label} {ps_clk_index}>, <&{clock_chip_label} 1>"
+        )
+        clkgen_clock_names = '"s_axi_aclk", "clkin1"'
         rx_clkgen_node = (
             f"\t&{rx_clkgen_label} {{\n"
+            "\t\t/delete-property/ clocks;\n"
             '\t\tcompatible = "adi,axi-clkgen-2.00.a";\n'
             "\t\t#clock-cells = <0>;\n"
             f'\t\tclock-output-names = "{rx_clkgen_label}";\n'
-            '\t\tclock-names = "clkin1", "s_axi_aclk";\n'
+            f"\t\tclocks = {clkgen_clocks};\n"
+            f"\t\tclock-names = {clkgen_clock_names};\n"
             "\t};"
         )
         tx_clkgen_node = (
             f"\t&{tx_clkgen_label} {{\n"
+            "\t\t/delete-property/ clocks;\n"
             '\t\tcompatible = "adi,axi-clkgen-2.00.a";\n'
             "\t\t#clock-cells = <0>;\n"
             f'\t\tclock-output-names = "{tx_clkgen_label}";\n'
-            '\t\tclock-names = "clkin1", "s_axi_aclk";\n'
-            "\t};"
-        )
-
-        # --- Misc fixed-clock node (provides reference clock) ---
-        misc_clk_node = (
-            "\t&misc_clk_0 {\n"
-            '\t\tcompatible = "fixed-clock";\n'
-            "\t\t#clock-cells = <0>;\n"
-            f"\t\tclock-frequency = <{misc_clk_hz}>;\n"
+            f"\t\tclocks = {clkgen_clocks};\n"
+            f"\t\tclock-names = {clkgen_clock_names};\n"
             "\t};"
         )
 
+        # ``misc_clk_0`` is no longer referenced now that clkgen
+        # points at AD9528 — emit no overlay for it.
         extra_before: list[str] = [
-            misc_clk_node,
             rx_clkgen_node,
             tx_clkgen_node,
             rx_xcvr_node,

test/devices/fixtures/adrv9371_zc706_xsa_reference.dts

@@ -132,22 +132,21 @@
 	};
 };
 
-	&misc_clk_0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <245760000>;
-	};
 	&axi_ad9371_rx_clkgen {
+		/delete-property/ clocks;
 		compatible = "adi,axi-clkgen-2.00.a";
 		#clock-cells = <0>;
 		clock-output-names = "axi_ad9371_rx_clkgen";
-		clock-names = "clkin1", "s_axi_aclk";
+		clocks = <&clkc 15>, <&clk0_ad9528 1>;
+		clock-names = "s_axi_aclk", "clkin1";
 	};
 	&axi_ad9371_tx_clkgen {
+		/delete-property/ clocks;
 		compatible = "adi,axi-clkgen-2.00.a";
 		#clock-cells = <0>;
 		clock-output-names = "axi_ad9371_tx_clkgen";
-		clock-names = "clkin1", "s_axi_aclk";
+		clocks = <&clkc 15>, <&clk0_ad9528 1>;
+		clock-names = "s_axi_aclk", "clkin1";
 	};
 	&axi_ad9371_rx_xcvr {
 		compatible = "adi,axi-adxcvr-1.0";