test(hw, adrv9371): TODO update — adxcvr-rewire hangs boot, reverted

Commit 607663b rewired ``axi_ad9371_{rx,tx}_xcvr`` +
``axi_ad9371_{rx,tx}_clkgen`` to structurally match bq's working
SD-card DT node-for-node (adxcvr points directly at AD9528 ch1,
clkgen drives off AD9528 ch1 rather than a misc_clk_0
fixed-clock overlay, adds ``adi,sys-clk-select``,
``adi,out-clk-select``, ``adi,use-lpm-enable``).

Decompiled DTB confirmed the shape matched the reference — but
bq never reached ``@analog`` prompt on boot; kernel hung
post-JESD, pre-userspace, with no UART captured because
``debug_write_boot_log`` was off on this leg.

Reverted in 3aa509a.  Document the attempt in the TODO with the
concrete next step: enable UART log capture and rerun the same
rewire, then diagnose the hang from the kernel trace.

Author: tfcollins

test/hw/test_adrv9371_zc706_hw.py

@@ -172,22 +172,25 @@ def test_adrv9371_zc706_xsa_hw(board, built_kernel_image_zynq, tmp_path):
     # / clkgen platform drivers never complete probe ("deferred
     # probe pending" in dmesg), so the TPL ADC has a live SerDes
     # upstream but no active Linux driver telling the AXI DMA to
-    # collect samples.  Root cause: ADRV937xBuilder points
-    # ``axi_ad9371_rx_xcvr`` at ``<&axi_ad9371_rx_clkgen>`` (both
-    # for conv and div40), but the clkgen itself never gets a
-    # probe-complete message — deferred-probe chain.
+    # collect samples.
     #
-    # The Kuiper reference DT bypasses the clkgen for this design:
-    # ``axi-adxcvr-rx@44a60000 { clocks = <&clk0_ad9528 1>;
-    # clock-names = "conv"; adi,sys-clk-select = <0>;
-    # adi,out-clk-select = <3>; adi,use-lpm-enable; }`` — it
-    # uses AD9528 channel 1 (FMC_CLK) directly as the conv clock
-    # and omits div40.
+    # Attempted fix (commit 607663b — REVERTED in 3aa509a):
+    # rewired ``axi_ad9371_{rx,tx}_xcvr`` to point directly at
+    # ``<&clk0_ad9528 1>`` (FMC_CLK) for ``conv`` with no ``div40``,
+    # added ``adi,sys-clk-select=<0>``, ``adi,out-clk-select=<3>``,
+    # ``adi,use-lpm-enable``, and wired ``axi_ad9371_{rx,tx}_clkgen``
+    # to ``<&clkc 15>, <&clk0_ad9528 1>`` instead of the
+    # ``misc_clk_0`` fixed-clock overlay.  Decompiled DTB matched
+    # the reference node-for-node on adxcvr/clkgen — but bq never
+    # reached ``@analog`` prompt on boot (kernel hung post-JESD
+    # pre-userspace).  The rewire is still directionally correct
+    # but triggers a kernel hang we can't diagnose without a direct
+    # UART capture, so reverted.
     #
-    # Re-wiring ADRV937xBuilder's clock graph to match that is the
-    # next step — bigger change than what fit in this series, so
-    # parking here with the DT improvements landed and capture
-    # still deferred.
+    # Next step: enable ``debug_write_boot_log: true`` on the bq
+    # direct YAML and rerun the 607663b rewire to capture the UART
+    # trace past the hang; then address whatever oops/loop the
+    # kernel reveals.
 
 
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