feat: add draw support for ADF4382 and fix ADF4030 drawing

tfcollins · tfcollins · commit 6a1962aa3660 · 2026-04-23T19:47:11.000-04:00
diff --git a/adijif/plls/__init__.py b/adijif/plls/__init__.py
@@ -1,3 +1,3 @@
 """ADI JIF PLL models."""
 
-supported_parts = ["adf4371", "adf4382"]
+supported_parts = ["adf4371", "adf4382", "adf4030"]
diff --git a/adijif/plls/adf4030.py b/adijif/plls/adf4030.py
@@ -8,8 +8,139 @@
 from adijif.plls.pll import pll
 from adijif.solvers import CpoExpr, GK_Intermediate
 
+from adijif.draw import Layout, Node
+
+
+class adf4030_drawer(object):
+    """ADF4030 diagram drawer."""
+
+    def _init_diagram(self) -> None:
+        """Initialize diagram with PLL block."""
+
+        self._diagram_output_dividers = []
+
+        self.ic_diagram_node = Node("ADF4030")
+
+        rdiv = Node("R", ntype="divider")
+        self.ic_diagram_node.add_child(rdiv)
+
+        pfd = Node("PFD", ntype="phase-frequency-detector")
+        self.ic_diagram_node.add_child(pfd)
+
+        charge_pump = Node("CP", ntype="charge-pump")
+        self.ic_diagram_node.add_child(charge_pump)
+
+        loop_filter = Node("LF", ntype="loop-filter")
+        self.ic_diagram_node.add_child(loop_filter)
+
+        vco = Node("VCO", ntype="vco")
+        self.ic_diagram_node.add_child(vco)
+
+        ndiv = Node("N", ntype="divider")
+        self.ic_diagram_node.add_child(ndiv)
+
+        output_dividers = Node("Output Dividers", ntype="shell")
+        self.ic_diagram_node.add_child(output_dividers)
+
+        # Connections
+        self.ic_diagram_node.add_connection({
+            "from": rdiv,
+            "to": pfd,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": pfd,
+            "to": charge_pump,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": charge_pump,
+            "to": loop_filter,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": loop_filter,
+            "to": vco,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": vco,
+            "to": ndiv,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": ndiv,
+            "to": pfd,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": vco,
+            "to": output_dividers,
+        })
+
+    def _update_diagram(self, config: Dict) -> None:
+        """Update diagram with new dividers."""
+
+        keys = config.keys()
+        output_dividers = self.ic_diagram_node.get_child("Output Dividers")
+        for key in keys:
+            if "o_div" in key and key not in self._diagram_output_dividers:
+                od_node = Node(key, ntype="divider")
+                output_dividers.add_child(od_node)
+                self.ic_diagram_node.add_connection({
+                    "from": output_dividers,
+                    "to": od_node,
+                })
+            else:
+                raise Exception("Unexpected config key: {}".format(key))
+            
+    def draw(self, lo: Layout = None) -> Union[str, Layout]:
+        """Draw diagram with configuration.
+
+        Args:
+            lo (Layout): Diagram layout object
+
+        Returns:
+            Layout: Diagram layout object
+        """
+        if not self._saved_solution:
+            raise Exception("No solution to draw. Must call solve first")
+        
+        system_draw = lo is not None
+        if not system_draw:
+            lo = Layout("ADF4030 Diagram")
+        else:
+            assert isinstance(lo, Layout), "Layout object must be provided for system drawing"
+        lo.add_node(self.ic_diagram_node)
+
+        ref_in = Node("REF_IN", ntype="input")
+        rdiv = self.ic_diagram_node.get_child("R")
+        lo.add_connection({
+            "from": ref_in,
+            "to": rdiv,
+            "rate": 100e6,  # TODO: Get actual rate
+        })
+
+        # Update node values
+        node = self.ic_diagram_node.get_child("R")
+        node.value = str(self._saved_solution["r"])
+        node = self.ic_diagram_node.get_child("N")
+        node.value = str(self._saved_solution["n"])
+        # for clk in self._clk_names:
+        #     od_node = self.ic_diagram_node.get_child(f"o_div_{clk}_adf4030")
+        #     od_node.value = str(self._saved_solution[f"o_div_{clk}_adf4030"])
+        for key, val in self._saved_solution["output_clocks"].items():
+            div = Node(key, ntype="divider")
+            div.value = str(val["divider"])
+            lo.add_node(div)
+            lo.add_connection({
+                "from": self.ic_diagram_node.get_child("Output Dividers"),
+                "to": div,
+                "rate": self._saved_solution["vco"] / val["divider"],
+            })
+
+        if system_draw:
+            return lo.draw()
+        
+        return lo.draw()
+
+
+class adf4030(pll, adf4030_drawer):
 
-class adf4030(pll):
     """ADF4030 PLL model.
 
     This model currently supports all divider configurations
@@ -157,6 +288,8 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
 
         config["output_clocks"] = output_config
 
+        self._saved_solution = config
+
         return config
 
     def _setup_solver_constraints(
@@ -322,3 +455,4 @@ def set_requested_clocks(
             self._add_equation(
                 self.config[o_div_name] * out_freq[i] == self.config["vco"],
             )
+
diff --git a/adijif/plls/adf4382.py b/adijif/plls/adf4382.py
@@ -5,6 +5,7 @@
 from docplex.cp.modeler import if_then
 from docplex.cp.solution import CpoSolveResult  # type: ignore
 
+from adijif.draw import Layout, Node
 from adijif.plls.pll import pll
 from adijif.solvers import CpoExpr, GK_Intermediate, integer_var
 
@@ -21,7 +22,127 @@ def to_int(
         raise TypeError(f"Unsupported type: {type(value)}")
 
 
-class adf4382(pll):
+class adf4382_drawer(object):
+    """ADF4382 diagram drawer."""
+
+    def _init_diagram(self) -> None:
+        """Initialize diagram with PLL block."""
+
+        self._diagram_output_dividers = []
+
+        self.ic_diagram_node = Node("ADF4382")
+
+        doubler = Node("D", ntype="doubler")
+        self.ic_diagram_node.add_child(doubler)
+
+        rdiv = Node("R", ntype="divider")
+        self.ic_diagram_node.add_child(rdiv)
+
+        pfd = Node("PFD", ntype="phase-frequency-detector")
+        self.ic_diagram_node.add_child(pfd)
+
+        charge_pump = Node("CP", ntype="charge-pump")
+        self.ic_diagram_node.add_child(charge_pump)
+
+        loop_filter = Node("LF", ntype="loop-filter")
+        self.ic_diagram_node.add_child(loop_filter)
+
+        vco = Node("VCO", ntype="vco")
+        self.ic_diagram_node.add_child(vco)
+
+        ndiv = Node("N", ntype="divider")
+        self.ic_diagram_node.add_child(ndiv)
+
+        output_dividers = Node("Output Dividers", ntype="shell")
+        self.ic_diagram_node.add_child(output_dividers)
+        
+        od_node = Node("O", ntype="divider")
+        output_dividers.add_child(od_node)
+
+        # Connections
+        self.ic_diagram_node.add_connection({
+            "from": doubler,
+            "to": rdiv,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": rdiv,
+            "to": pfd,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": pfd,
+            "to": charge_pump,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": charge_pump,
+            "to": loop_filter,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": loop_filter,
+            "to": vco,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": vco,
+            "to": ndiv,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": ndiv,
+            "to": pfd,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": vco,
+            "to": output_dividers,
+        })
+        self.ic_diagram_node.add_connection({
+            "from": output_dividers,
+            "to": od_node,
+        })
+
+    def draw(self, lo: Layout = None) -> Union[str, Layout]:
+        """Draw diagram with configuration.
+
+        Args:
+            lo (Layout): Diagram layout object
+
+        Returns:
+            Layout: Diagram layout object
+        """
+        if not self._saved_solution:
+            raise Exception("No solution to draw. Must call solve first")
+        
+        system_draw = lo is not None
+        if not system_draw:
+            lo = Layout("ADF4382 Diagram")
+        else:
+            assert isinstance(lo, Layout), "Layout object must be provided for system drawing"
+            
+        lo.add_node(self.ic_diagram_node)
+
+        ref_in = Node("REF_IN", ntype="input")
+        doubler = self.ic_diagram_node.get_child("D")
+        lo.add_connection({
+            "from": ref_in,
+            "to": doubler,
+            "rate": 100e6,  # TODO: Get actual rate
+        })
+
+        # Update node values
+        node = self.ic_diagram_node.get_child("D")
+        node.value = str(self._saved_solution["d"])
+        node = self.ic_diagram_node.get_child("R")
+        node.value = str(self._saved_solution["r"])
+        node = self.ic_diagram_node.get_child("N")
+        node.value = str(self._saved_solution["n"])
+
+        output_dividers = self.ic_diagram_node.get_child("Output Dividers")
+        od_node = output_dividers.get_child("O")
+        od_node.value = str(self._saved_solution["o"])
+
+        if system_draw:
+            return lo.draw()
+        
+        return lo.draw()
+
+class adf4382(pll, adf4382_drawer):
     """ADF4382 PLL model.
 
     This model does not support fractional mode
@@ -316,6 +437,8 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
         vco = self.solution.get_kpis()["vco"]
         config["rf_out_frequency"] = vco / config["o"]
 
+        self._saved_solution = config
+
         return config
 
     def _setup_solver_constraints(
diff --git a/adijif/system_draw.py b/adijif/system_draw.py
@@ -36,13 +36,42 @@ def draw(self, config: Dict) -> str:
 
         self.clock.draw(lo)
 
+        # External PLLs (SYSREF and/or Direct)
+        if self.plls is not None:
+            if not isinstance(self.plls, list):
+                plls = [self.plls]
+            else:
+                plls = self.plls
+
+            for pll in plls:
+                pll.draw(lo)
+                
+        if hasattr(self, "plls_sysref") and self.plls_sysref is not None:
+            if not isinstance(self.plls_sysref, list):
+                plls_sysref = [self.plls_sysref]
+            else:
+                plls_sysref = self.plls_sysref
+
+            for pll in plls_sysref:
+                pll.draw(lo)
+
         # Converter
         assert self.converter is not None
         assert not isinstance(self.converter, list), (
             "Only one converter supported"
         )
 
         cnv_clocking = config["clock"]["output_clocks"].copy()
+        if "plls" in config:
+            for pll_cfg in config["plls"]:
+                if "output_clocks" in pll_cfg:
+                    cnv_clocking.update(pll_cfg["output_clocks"])
+        
+        # Also grab output_clocks from any ext plls in config directly
+        for key in config:
+            if "pll" in key and isinstance(config[key], dict) and "output_clocks" in config[key]:
+                cnv_clocking.update(config[key]["output_clocks"])
+
         for clk in cnv_clocking:
             rate = cnv_clocking[clk]["rate"]
             cnv_clocking[clk] = rate
diff --git a/examples/ad9084_rx_hmc7044_ext_pll_adf4382.py b/examples/ad9084_rx_hmc7044_ext_pll_adf4382.py
diff --git a/tests/test_adf4382.py b/tests/test_adf4382.py

Original file line number	Diff line number	Diff line change
`@@ -1,3 +1,3 @@`
`1`	`1`	`"""ADI JIF PLL models."""`
`2`	`2`
`3`		`-supported_parts = ["adf4371", "adf4382"]`
	`3`	`+supported_parts = ["adf4371", "adf4382", "adf4030"]`