Merge pull request #216 from analogdevicesinc/hal/draw

Author: tfcollins

adijif/clocks/ad9545.py

@@ -7,6 +7,7 @@
 import docplex.cp.modeler as mod
 
 from adijif.clocks.clock import clock
+from adijif.draw import Layout, Node
 from adijif.solvers import CpoSolveResult
 
 
@@ -198,8 +199,103 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
         for i in range(0, 10):
             config["q" + str(i)] = self._get_val(self.config["q" + str(i)])
 
+        self._saved_solution = config
+
         return config
 
+    def draw(self, lo: Layout = None) -> str:
+        """Draw clock tree diagram for AD9545.
+
+        Args:
+            lo: Layout for drawing
+
+        Returns:
+            str: SVG diagram string
+
+        Raises:
+            Exception: If no solution is saved
+        """
+        if not self._saved_solution:
+            raise Exception("No solution to draw. Must call solve first.")
+
+        config = self._saved_solution
+        system_draw = lo is not None
+        if not system_draw:
+            lo = Layout("AD9545 Example")
+        else:
+            assert isinstance(lo, Layout), "lo must be a Layout object"
+
+        ic_node = Node("AD9545")
+        lo.add_node(ic_node)
+
+        # Add active input references with R dividers
+        for i in range(4):
+            if self.input_refs[i] != 0:
+                r_val = config[f"r{i}"]
+                r_node = Node(f"R{i}", ntype="divider")
+                r_node.value = str(r_val)
+                ic_node.add_child(r_node)
+
+                if not system_draw:
+                    ref_node = Node(f"REF{i}", ntype="input")
+                    lo.add_node(ref_node)
+                    lo.add_connection(
+                        {
+                            "from": ref_node,
+                            "to": r_node,
+                            "rate": self.input_refs[i],
+                        }
+                    )
+
+        # Add PLLs
+        for i in range(2):
+            if self.PLL_used[i]:
+                pll_rate = config[f"PLL{i}"].get("rate_hz", 0)
+                pll_node = Node(f"PLL{i}", ntype="voltage-controlled-oscillator")
+                pll_node.shape = "circle"
+                ic_node.add_child(pll_node)
+
+                # Connect active input R dividers to PLL
+                for j in range(4):
+                    if self.input_refs[j] != 0:
+                        r_node = ic_node.get_child(f"R{j}")
+                        pll_in_rate = self.input_refs[j] / config[f"r{j}"]
+                        ic_node.add_connection(
+                            {"from": r_node, "to": pll_node, "rate": pll_in_rate}
+                        )
+
+        # Add output Q dividers
+        out_dividers = Node("Output Dividers", ntype="shell")
+        ic_node.add_child(out_dividers)
+
+        for i in range(10):
+            if self.out_freqs[i] != 0:
+                q_val = config[f"q{i}"]
+                q_node = Node(f"Q{i}", ntype="divider")
+                q_node.value = str(q_val)
+                out_dividers.add_child(q_node)
+
+                # Determine which PLL feeds this output
+                pll_idx = 0 if i <= 5 else 1
+                if self.PLL_used[pll_idx]:
+                    pll_node = ic_node.get_child(f"PLL{pll_idx}")
+                    pll_rate = config[f"PLL{pll_idx}"].get("rate_hz", 0)
+                    ic_node.add_connection(
+                        {"from": pll_node, "to": q_node, "rate": pll_rate}
+                    )
+
+                out_node = Node(f"OUT{i}", ntype="out_clock_connected")
+                lo.add_node(out_node)
+                lo.add_connection(
+                    {
+                        "from": q_node,
+                        "to": out_node,
+                        "rate": self.out_freqs[i],
+                    }
+                )
+
+        return lo.draw()
+
     def _setup_solver_constraints(
         self, input_refs: List[int], out_freqs: List[int]
     ) -> None:

adijif/clocks/ltc6953.py

@@ -5,6 +5,7 @@
 from docplex.cp.solution import CpoSolveResult  # type: ignore
 
 from adijif.clocks.clock import clock
+from adijif.draw import Layout, Node
 from adijif.solvers import CpoExpr, GK_Intermediate
 
 
@@ -421,6 +422,74 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
 
         return config
 
+    def draw(self, lo: Layout = None) -> str:
+        """Draw clock tree diagram for LTC6953.
+
+        Args:
+            lo: Layout for drawing
+
+        Returns:
+            str: SVG diagram string
+
+        Raises:
+            Exception: If no solution is saved
+        """
+        if not self._saved_solution:
+            raise Exception("No solution to draw. Must call solve first.")
+
+        system_draw = lo is not None
+        if not system_draw:
+            lo = Layout("LTC6953 Example")
+        else:
+            assert isinstance(lo, Layout), "lo must be a Layout object"
+
+        ic_node = Node("LTC6953")
+        lo.add_node(ic_node)
+
+        # Output dividers inside IC
+        out_dividers_node = Node("Output Dividers", ntype="shell")
+        ic_node.add_child(out_dividers_node)
+
+        if not system_draw:
+            ref_in = Node("REF_IN", ntype="input")
+            lo.add_node(ref_in)
+        else:
+            ref_name = None
+            for key in self._saved_solution.keys():
+                if "input_ref" in key.lower():
+                    ref_name = key
+                    break
+            if ref_name:
+                to_node = lo.get_node(ref_name)
+                from_node = lo.get_connection(to=to_node.name)
+                assert from_node, "No connection found"
+                assert isinstance(from_node, list), "Connection must be a list"
+                assert len(from_node) == 1, "Only one connection allowed"
+                ref_in = from_node[0]["from"]
+                lo.remove_node(to_node.name)
+            else:
+                ref_in = Node("REF_IN", ntype="input")
+                lo.add_node(ref_in)
+
+        input_ref = self._saved_solution["input_ref"]
+        lo.add_connection({"from": ref_in, "to": ic_node, "rate": input_ref})
+
+        # Add each output clock with its divider
+        for i, (clk_name, clk_cfg) in enumerate(
+            self._saved_solution["output_clocks"].items()
+        ):
+            div_node = Node(f"D{i}", ntype="divider")
+            div_node.value = str(int(clk_cfg["divider"]))
+            out_dividers_node.add_child(div_node)
+
+            clk_node = Node(clk_name, ntype="out_clock_connected")
+            lo.add_node(clk_node)
+            lo.add_connection(
+                {"from": div_node, "to": clk_node, "rate": clk_cfg["rate"]}
+            )
+
+        return lo.draw()
+
     def _setup_solver_constraints(self, input_ref: int) -> None:
         """Apply constraints to solver model.
 

adijif/converters/ad9081.py

@@ -7,6 +7,7 @@
 
 from ..solvers import GEKKO, CpoModel, CpoSolveResult  # type: ignore
 from .ad9081_dp import ad9081_dp_rx, ad9081_dp_tx
+from .ad9081_draw import ad9081_rx_draw, ad9081_tx_draw
 from .ad9081_util import _load_rx_config_modes, _load_tx_config_modes
 from .adc import adc
 from .converter import converter
@@ -307,7 +308,7 @@ def get_required_clocks(self) -> List:
         return [clk, self.config["sysref"]]
 
 
-class ad9081_rx(adc, ad9081_core):
+class ad9081_rx(ad9081_rx_draw, adc, ad9081_core):
     """AD9081 Receive model."""
 
     name = "AD9081_RX"
@@ -424,7 +425,7 @@ def _check_valid_internal_configuration(self) -> None:
             raise Exception("Decimation not valid")
 
 
-class ad9081_tx(dac, ad9081_core):
+class ad9081_tx(ad9081_tx_draw, dac, ad9081_core):
     """AD9081 Transmit model."""
 
     name = "AD9081_TX"