Commit 26d49ef
committed
mimxrt/sdcard: Add cache coherency operations for DMA transfers.
Add explicit data cache management to ensure DMA transfers work correctly
on systems with data cache enabled (e.g., MIMXRT1170).
For writes: Clean cache to RAM before transfer so DMA reads correct data.
For reads: Clean and invalidate cache before transfer, then invalidate
again after transfer completes to discard any speculative cache line
fills that may have occurred during the DMA.
Also fix writeblocks to use MP_BUFFER_READ (reading from buffer to write
to card) and update read/writeblocks to raise OSError on failure.
Signed-off-by: Andrew Leech <[email protected]>1 parent 2f1b12e commit 26d49ef
2 files changed
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-13
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