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mimxrt/PHYBOARD_RT1170: Add phyBOARD-RT1170 Development Kit board support.
Adds board support for PHYTEC phyBOARD-RT1170 Development Kit featuring MIMXRT1176 dual-core (Cortex-M7/M4), 64MB SDRAM, 16MB QSPI Flash, dual Gigabit Ethernet (DP83867 RGMII + KSZ8081 RMII), USB 2.0, MIPI-DSI/CSI, audio codec, CAN FD, RS-232, microSD, and M.2 Key E connector. Signed-off-by: Andrew Leech <[email protected]>
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‎ports/mimxrt/boards/PHYBOARD_RT1170/board.json‎

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{
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"deploy": [
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"../deploy_mimxrt.md"
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],
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"docs": "",
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"features": [
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"Dual-core ARM Cortex-M7/M4",
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"32MB SDRAM",
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"512MB QSPI Flash",
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"Dual Gigabit Ethernet (DP83867 + KSZ8081)",
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"USB 2.0 High-Speed Host and Device",
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"MIPI-DSI Display Interface",
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"MIPI-CSI Camera Interface",
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"Audio Codec (TLV320AIC3110)",
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"6-axis Accelerometer (ICM-40627)",
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"CAN FD Interface",
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"RS-232 Serial Interface",
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"microSD Card Slot",
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"M.2 Key E Connector (WiFi/Bluetooth)",
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"JTAG Debug Interface",
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"User Button, Power/Wake/Reset Buttons",
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"RGB User LEDs",
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"Multiple UART/I2C/SPI Interfaces",
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"PWM/ADC Channels",
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"I2C EEPROM",
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"40-pin Expansion Connector",
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"Development Kit includes Carrier Board"
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],
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"images": [],
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"mcu": "mimxrt",
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"product": "phyBOARD-RT1170 Development Kit",
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"thumbnail": "",
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"url": "https://www.phytec.com/product/phyboard-rt1170-development-kit/",
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"vendor": "PHYTEC"
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}

‎ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py‎

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include("../manifest.py")
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require("bundle-networking")
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include("$(MPY_DIR)/extmod/asyncio/manifest.py")
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# Board-specific drivers
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require("icm40627")
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# Freeze board initialization module
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module("board.py")

‎ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h‎

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#define MICROPY_HW_BOARD_NAME "phyBOARD-RT1170 Development Kit"
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#define MICROPY_HW_MCU_NAME "MIMXRT1176DVMAA"
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#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-phyboard"
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#define MICROPY_EVENT_POLL_HOOK \
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do { \
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extern void mp_handle_pending(bool); \
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mp_handle_pending(true); \
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} while (0);
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// phyBOARD-RT1170 SoM onboard LEDs (red and green from phyCORE SoM)
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// Carrier board provides additional RGB LEDs via GPIO
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#define MICROPY_HW_LED1_PIN (pin_GPIO_LPSR_07) // SoM Red LED
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#define MICROPY_HW_LED2_PIN (pin_GPIO_LPSR_08) // SoM Green LED
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) // LEDs are active low
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
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// phyBOARD carrier board RGB LEDs
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#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_14) // Carrier Red LED
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#define MICROPY_HW_LED4_PIN (pin_GPIO_LPSR_13) // Carrier Green LED
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#define MICROPY_HW_NUM_PIN_IRQS (6 * 32)
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// Define mapping hardware UART # to logical UART #
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// phyBOARD-RT1170 UART interfaces
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// LPUART1 -> 0 (GPIO_AD_24/25) - Primary debug/console (SoM)
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// LPUART2 -> 1 (GPIO_DISP_B2_10/11/12/13) - Carrier board
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// LPUART3 -> 2 (GPIO_AD_30/31) - General purpose (SoM)
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// LPUART5 -> 3 (GPIO_AD_28/29) - Expansion (SoM)
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// LPUART6 -> 4 (GPIO_EMC_B1_40/41) - Console UART (FT2232H - Carrier)
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// LPUART7 -> 5 (GPIO_DISP_B2_06/07) - General purpose (SoM)
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// LPUART8 -> 6 (GPIO_AD_02/03/04/05) - RS-232 (Carrier)
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 6, 7, 8 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_24_LPUART1_TXD }, { IOMUXC_GPIO_AD_25_LPUART1_RXD }, \
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{ IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD }, { IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD }, \
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{ IOMUXC_GPIO_AD_30_LPUART3_TXD }, { IOMUXC_GPIO_AD_31_LPUART3_RXD }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_28_LPUART5_TXD }, { IOMUXC_GPIO_AD_29_LPUART5_RXD }, \
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{ IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD }, { IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD }, \
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{ IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD }, { IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD }, \
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{ IOMUXC_GPIO_AD_02_LPUART8_TXD }, { IOMUXC_GPIO_AD_03_LPUART8_RXD }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 },
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#define IOMUX_TABLE_UART_CTS_RTS \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B }, { IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_04_LPUART8_CTS_B }, { IOMUXC_GPIO_AD_05_LPUART8_RTS_B }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 },
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// Define the mapping hardware SPI # to logical SPI #
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// phyCORE SoM basic SPI interfaces available on connector
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// LPSPI1 -> 0 (GPIO_AD_28/29/30/31)
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// LPSPI2 -> 1 (GPIO_AD_24/25/26/27)
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#define MICROPY_HW_SPI_INDEX { 1, 2 }
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#define IOMUX_TABLE_SPI \
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{ IOMUXC_GPIO_AD_28_LPSPI1_SCK }, { IOMUXC_GPIO_AD_29_LPSPI1_PCS0 }, \
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{ IOMUXC_GPIO_AD_30_LPSPI1_SOUT }, { IOMUXC_GPIO_AD_31_LPSPI1_SIN }, \
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{ IOMUXC_GPIO_AD_24_LPSPI2_SCK }, { IOMUXC_GPIO_AD_25_LPSPI2_PCS0 }, \
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{ IOMUXC_GPIO_AD_26_LPSPI2_SOUT }, { IOMUXC_GPIO_AD_27_LPSPI2_SIN }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 },
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
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kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
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kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
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// Define the mapping hardware I2C # to logical I2C #
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// phyBOARD-RT1170 I2C interfaces
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// LPI2C1 -> 0 (GPIO_AD_32/33) - EEPROM (SoM)
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// LPI2C2 -> 1 (GPIO_AD_18/19) - EEPROM + Accelerometer (Carrier)
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// LPI2C3 -> 2 (GPIO_DISP_B2_10/11) - Reserved (SoM)
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// LPI2C5 -> 3 (GPIO_LPSR_08/09, GPIO_AD_26/27) - Audio Codec + Accelerometer (Carrier)
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#define MICROPY_HW_I2C_INDEX { 1, 2, 3, 5 }
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#define IOMUX_TABLE_I2C \
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{ IOMUXC_GPIO_AD_32_LPI2C1_SCL }, { IOMUXC_GPIO_AD_33_LPI2C1_SDA }, \
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{ IOMUXC_GPIO_AD_18_LPI2C2_SCL }, { IOMUXC_GPIO_AD_19_LPI2C2_SDA }, \
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{ IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL }, { IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_LPSR_08_LPI2C5_SDA }, { IOMUXC_GPIO_LPSR_09_LPI2C5_SCL }, \
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{ 0 }, { 0 },
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#define MICROPY_PY_MACHINE_I2S (1)
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#define MICROPY_HW_I2S_NUM (1)
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#define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 }
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#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx, kDmaRequestMuxSai3Rx, kDmaRequestMuxSai4Rx }
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#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx, kDmaRequestMuxSai3Tx, kDmaRequestMuxSai4Tx }
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#define I2S_WM8960_RX_MODE (1)
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#define I2S_AUDIO_PLL_CLOCK (4U)
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#define DMAMUX DMAMUX0
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#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
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{ \
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.hw_id = _hwid, \
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.fn = _fn, \
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.mode = _mode, \
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.name = MP_QSTR_##_pin, \
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.iomux = {_iomux}, \
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}
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#define I2S_GPIO_MAP \
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{ \
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I2S_GPIO(1, MCK, TX, GPIO_AD_17, IOMUXC_GPIO_AD_17_SAI1_MCLK), \
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I2S_GPIO(1, SCK, RX, GPIO_AD_19, IOMUXC_GPIO_AD_19_SAI1_RX_BCLK), \
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I2S_GPIO(1, WS, RX, GPIO_AD_18, IOMUXC_GPIO_AD_18_SAI1_RX_SYNC), \
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I2S_GPIO(1, SD, RX, GPIO_AD_20, IOMUXC_GPIO_AD_20_SAI1_RX_DATA00), \
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I2S_GPIO(1, SCK, TX, GPIO_AD_22, IOMUXC_GPIO_AD_22_SAI1_TX_BCLK), \
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I2S_GPIO(1, WS, TX, GPIO_AD_23, IOMUXC_GPIO_AD_23_SAI1_TX_SYNC), \
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I2S_GPIO(1, SD, TX, GPIO_AD_21, IOMUXC_GPIO_AD_21_SAI1_TX_DATA00), \
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}
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// USDHC1 (SDCARD)
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#define MICROPY_PY_MACHINE_SDCARD 0
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#if MICROPY_PY_MACHINE_SDCARD
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#define USDHC_DUMMY_PIN NULL, 0
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#define MICROPY_USDHC1 \
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{ \
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.cmd = {GPIO_SD_B1_00_USDHC1_CMD}, \
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.clk = { GPIO_SD_B1_01_USDHC1_CLK }, \
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.cd_b = { USDHC_DUMMY_PIN }, \
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.data0 = { GPIO_SD_B1_02_USDHC1_DATA0 }, \
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.data1 = { GPIO_SD_B1_03_USDHC1_DATA1 }, \
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.data2 = { GPIO_SD_B1_04_USDHC1_DATA2 }, \
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.data3 = { GPIO_SD_B1_05_USDHC1_DATA3 }, \
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}
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#define USDHC_DATA3_PULL_DOWN_ON_BOARD (1)
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#endif
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// Network definitions
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// phyBOARD-RT1170 Dual Ethernet configuration
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// Port 0: KSZ8081 100Mbps RMII PHY on carrier board (PBA-C-26)
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// Port 1: DP83867 1Gbps RGMII PHY on phyCORE SoM
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// Primary Ethernet (100M RMII) - KSZ8081 on carrier board
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#define ENET_PHY_ADDRESS (1) // KSZ8081 PHY address 001b
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#define ENET_PHY KSZ8081
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#define ENET_PHY_OPS phyksz8081_ops
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// ENET RMII pin configuration - connected to carrier board KSZ8081
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#define IOMUX_TABLE_ENET \
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{ IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \
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{ IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \
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{ IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0, 0x06u }, \
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{ IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0, 0x02u }, \
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{ IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0, 0x02u }, \
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{ IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0, 0x06u }, \
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{ IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1, 0x03u }, \
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{ IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0, 0x06u }, \
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{ IOMUXC_GPIO_AD_33_ENET_MDIO, 0, 0x06u }, \
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{ IOMUXC_GPIO_AD_32_ENET_MDC, 0, 0x06u },
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// Enable secondary Ethernet port (1G RGMII on SoM)
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#define ENET_DUAL_PORT (1)
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// Secondary Ethernet (1G RGMII) - DP83867 on phyCORE SoM
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#define ENET_1_PHY_ADDRESS (0)
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#define ENET_1_PHY DP83867
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#define ENET_1_PHY_OPS phydp83867_ops
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// ENET_1G RGMII pin configuration - full RGMII pins for Gigabit operation
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#define IOMUX_TABLE_ENET_1 \
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{ IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, 0, 0x08U }, \
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{ IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, 0, 0x0CU }, \
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{ IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, 0, 0x0CU }, \
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{ IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, 0, 0x0CU }, \
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{ IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, 0, 0x0CU }, \
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{ IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, 0, 0x0CU }, \
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{ IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, 0, 0x0CU }, \
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{ IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, 0, 0x06u }, \
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{ IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, 0, 0x06u },
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// --- SEMC --- //
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#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
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#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
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#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
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#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
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#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
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#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
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#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
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#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
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#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
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#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
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#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
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#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
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#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
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#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
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#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
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#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
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#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
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#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
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#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
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#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
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#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
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#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
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#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
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#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
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#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
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#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
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#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
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#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
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#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
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#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
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#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
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#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
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#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
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#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
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#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
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#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_B1_28_SEMC_WE
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#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
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#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
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#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
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#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
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#define MIMXRT_IOMUXC_SEMC_DATA16 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
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#define MIMXRT_IOMUXC_SEMC_DATA17 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
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#define MIMXRT_IOMUXC_SEMC_DATA18 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
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#define MIMXRT_IOMUXC_SEMC_DATA19 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
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#define MIMXRT_IOMUXC_SEMC_DATA20 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
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#define MIMXRT_IOMUXC_SEMC_DATA21 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
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#define MIMXRT_IOMUXC_SEMC_DATA22 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
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#define MIMXRT_IOMUXC_SEMC_DATA23 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
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#define MIMXRT_IOMUXC_SEMC_DM02 IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
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#define MIMXRT_IOMUXC_SEMC_DATA24 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
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#define MIMXRT_IOMUXC_SEMC_DATA25 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
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#define MIMXRT_IOMUXC_SEMC_DATA26 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
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#define MIMXRT_IOMUXC_SEMC_DATA27 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
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#define MIMXRT_IOMUXC_SEMC_DATA28 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
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#define MIMXRT_IOMUXC_SEMC_DATA29 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
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#define MIMXRT_IOMUXC_SEMC_DATA30 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
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#define MIMXRT_IOMUXC_SEMC_DATA31 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
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#define MIMXRT_IOMUXC_SEMC_DM03 IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
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#define MIMXRT_IOMUXC_SEMC_DQS4 IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4
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#if MICROPY_PY_MACHINE_I2S
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#define MICROPY_BOARD_ROOT_POINTERS \
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struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM];
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#endif
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// AUTOGENERATED by update.py from copier
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#define MICROPY_HW_USB_CDC_NUM (2)
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#define MICROPY_HW_USB_MSC (0)
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#define MICROPY_HW_USB_HID (0)
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#define MICROPY_HW_USB_MANUFACTURER_STRING "PHYTEC"
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#define MICROPY_HW_USB_PRODUCT_HS_STRING "phyBOARD-RT1170 Development Kit"
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#define MICROPY_HW_USB_PRODUCT_FS_STRING "phyBOARD-RT1170 Development Kit"
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#define MICROPY_HW_USB_CONFIGURATION_HS_STRING "phyBOARD Config"
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#define MICROPY_HW_USB_INTERFACE_HS_STRING "phyBOARD Interface"
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#define MICROPY_HW_USB_CONFIGURATION_FS_STRING "phyBOARD Config"
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#define MICROPY_HW_USB_INTERFACE_FS_STRING "phyBOARD Interface"
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#define MBOOT_USBD_MANUFACTURER_STRING "PHYTEC"
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#define MBOOT_USBD_PRODUCT_STRING "phyBOARD Boot"
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// phyBOARD-RT1170 Development Kit hardware features
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// Onboard EEPROM (M24C32 - 32Kbit)
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#define MICROPY_HW_EEPROM_I2C_BUS (0) // On LPI2C1 (SoM)
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#define MICROPY_HW_EEPROM_ADDR (0x50)
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// Carrier board peripherals
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// Audio Codec: TLV320AIC3110 on LPI2C5 (I2C address: 0x18)
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// Accelerometer: ICM-40627 on LPI2C2 (I2C address: 0x6B)
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// CAN Interface: CAN3 (GPIO_LPSR_00/01)
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// RS-232 Serial: LPUART8 (GPIO_AD_02/03/04/05)
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// User Button: GPIO_AD_35
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// RGB LEDs: GPIO_AD_14 (red), GPIO_LPSR_13 (green)
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// microSD Card Slot: USDHC1
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// M.2 Connector (Key E): WiFi/Bluetooth modules
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// Basic ADC channels available on connector
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#define MICROPY_HW_ADC_NUM_CHANNELS (16) // GPIO_AD domain pins

‎ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk‎

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MCU_SERIES = MIMXRT1176
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MCU_VARIANT = MIMXRT1176DVMAA
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MCU_CORE = _cm7
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MICROPY_FLOAT_IMPL = double
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MICROPY_HW_FLASH_TYPE ?= qspi_nor_flash
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MICROPY_HW_FLASH_SIZE ?= 0x1000000 # 16MB
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MICROPY_HW_FLASH_RESERVED ?= 0x100000 # 1MB CM4 Code address space
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MICROPY_HW_FLASH_CLK = kFlexSpiSerialClk_100MHz
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MICROPY_HW_FLASH_QE_CMD = 0x31
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MICROPY_HW_FLASH_QE_ARG = 0x02
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# phyCORE SoM flash timing - use loopback from DQS pad for better signal integrity
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MICROPY_HW_FLASH_DQS = kFlexSPIReadSampleClk_LoopbackFromDqsPad
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MICROPY_HW_SDRAM_AVAIL = 1
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MICROPY_HW_SDRAM_SIZE = 0x4000000 # 64MB
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MICROPY_PY_LWIP = 1
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MICROPY_PY_SSL = 1
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MICROPY_SSL_MBEDTLS = 1
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MICROPY_PY_OPENAMP = 1
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MICROPY_PY_OPENAMP_REMOTEPROC = 1
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FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
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CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 \
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-DMIMXRT117x_SERIES \
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-DENET_ENHANCEDBUFFERDESCRIPTOR_MODE=1 \
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-DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \
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-DUSB1_BASE=USB_OTG1_BASE \
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-DUSB2_BASE=USB_OTG2_BASE

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