Skip to content

Commit 99d763b

Browse files
pi-anlpi-anl
committed
mimxrt: Add PHYBOARD-RT1170 board support.
Adds board support for PHYTEC phyBOARD-RT1170 Development Kit featuring MIMXRT1176 dual-core (Cortex-M7/M4), 64MB SDRAM, 16MB QSPI Flash, dual Gigabit Ethernet (DP83867 RGMII + KSZ8081 RMII), USB 2.0, MIPI-DSI/CSI, audio codec, CAN FD, RS-232, microSD, and M.2 Key E connector. Signed-off-by: Andrew Leech <[email protected]>
1 parent 2762fe6 commit 99d763b

File tree

6 files changed

+496
-1
lines changed

6 files changed

+496
-1
lines changed

‎ports/mimxrt/boards/PHYBOARD_RT1170/board.json‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
{
2+
"deploy": [
3+
"../deploy_mimxrt.md"
4+
],
5+
"docs": "",
6+
"features": [
7+
"Audio Codec",
8+
"CAN",
9+
"Camera",
10+
"Display",
11+
"Dual-core",
12+
"Ethernet",
13+
"External Flash",
14+
"External RAM",
15+
"IMU",
16+
"RGB LED",
17+
"USB",
18+
"microSD"
19+
],
20+
"images": [],
21+
"mcu": "mimxrt",
22+
"product": "phyBOARD-RT1170 Development Kit",
23+
"thumbnail": "",
24+
"url": "https://www.phytec.com/product/phyboard-rt1170-development-kit/",
25+
"vendor": "PHYTEC"
26+
}

‎ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
include("../manifest.py")
2+
require("bundle-networking")
3+
include("$(MPY_DIR)/extmod/asyncio/manifest.py")

‎ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h‎

Lines changed: 308 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,308 @@
1+
#define MICROPY_HW_BOARD_NAME "phyBOARD-RT1170 Development Kit"
2+
#define MICROPY_HW_MCU_NAME "MIMXRT1176DVMAA"
3+
4+
#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-phyboard"
5+
6+
#define MICROPY_EVENT_POLL_HOOK \
7+
do { \
8+
extern void mp_handle_pending(bool); \
9+
mp_handle_pending(true); \
10+
} while (0);
11+
12+
// phyBOARD-RT1170 SoM onboard LEDs (red and green from phyCORE SoM)
13+
// Carrier board provides additional RGB LEDs via GPIO
14+
#define MICROPY_HW_LED1_PIN (pin_GPIO_LPSR_07) // SoM Red LED
15+
#define MICROPY_HW_LED2_PIN (pin_GPIO_LPSR_08) // SoM Green LED
16+
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) // LEDs are active low
17+
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
18+
19+
// phyBOARD carrier board RGB LEDs
20+
#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_14) // Carrier Red LED
21+
#define MICROPY_HW_LED4_PIN (pin_GPIO_LPSR_13) // Carrier Green LED
22+
23+
#define MICROPY_HW_NUM_PIN_IRQS (6 * 32)
24+
25+
// Define mapping hardware UART # to logical UART #
26+
// phyBOARD-RT1170 UART interfaces
27+
// LPUART1 -> 0 (GPIO_AD_24/25) - Primary debug/console (SoM)
28+
// LPUART2 -> 1 (GPIO_DISP_B2_10/11/12/13) - Carrier board
29+
// LPUART3 -> 2 (GPIO_AD_30/31) - General purpose (SoM)
30+
// LPUART5 -> 3 (GPIO_AD_28/29) - Expansion (SoM)
31+
// LPUART6 -> 4 (GPIO_EMC_B1_40/41) - Console UART (FT2232H - Carrier)
32+
// LPUART7 -> 5 (GPIO_DISP_B2_06/07) - General purpose (SoM)
33+
// LPUART8 -> 6 (GPIO_AD_02/03/04/05) - RS-232 (Carrier)
34+
35+
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
36+
#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 6, 7, 8 }
37+
38+
#define IOMUX_TABLE_UART \
39+
{ IOMUXC_GPIO_AD_24_LPUART1_TXD }, { IOMUXC_GPIO_AD_25_LPUART1_RXD }, \
40+
{ IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD }, { IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD }, \
41+
{ IOMUXC_GPIO_AD_30_LPUART3_TXD }, { IOMUXC_GPIO_AD_31_LPUART3_RXD }, \
42+
{ 0 }, { 0 }, \
43+
{ IOMUXC_GPIO_AD_28_LPUART5_TXD }, { IOMUXC_GPIO_AD_29_LPUART5_RXD }, \
44+
{ IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD }, { IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD }, \
45+
{ IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD }, { IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD }, \
46+
{ IOMUXC_GPIO_AD_02_LPUART8_TXD }, { IOMUXC_GPIO_AD_03_LPUART8_RXD }, \
47+
{ 0 }, { 0 }, \
48+
{ 0 }, { 0 }, \
49+
{ 0 }, { 0 }, \
50+
{ 0 }, { 0 },
51+
52+
#define IOMUX_TABLE_UART_CTS_RTS \
53+
{ 0 }, { 0 }, \
54+
{ IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B }, { IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B }, \
55+
{ 0 }, { 0 }, \
56+
{ 0 }, { 0 }, \
57+
{ 0 }, { 0 }, \
58+
{ 0 }, { 0 }, \
59+
{ 0 }, { 0 }, \
60+
{ IOMUXC_GPIO_AD_04_LPUART8_CTS_B }, { IOMUXC_GPIO_AD_05_LPUART8_RTS_B }, \
61+
{ 0 }, { 0 }, \
62+
{ 0 }, { 0 }, \
63+
{ 0 }, { 0 }, \
64+
{ 0 }, { 0 },
65+
66+
// Define the mapping hardware SPI # to logical SPI #
67+
// phyCORE SoM basic SPI interfaces available on connector
68+
// LPSPI1 -> 0 (GPIO_AD_28/29/30/31)
69+
// LPSPI2 -> 1 (GPIO_AD_24/25/26/27)
70+
71+
#define MICROPY_HW_SPI_INDEX { 1, 2 }
72+
73+
#define IOMUX_TABLE_SPI \
74+
{ IOMUXC_GPIO_AD_28_LPSPI1_SCK }, { IOMUXC_GPIO_AD_29_LPSPI1_PCS0 }, \
75+
{ IOMUXC_GPIO_AD_30_LPSPI1_SOUT }, { IOMUXC_GPIO_AD_31_LPSPI1_SIN }, \
76+
{ IOMUXC_GPIO_AD_24_LPSPI2_SCK }, { IOMUXC_GPIO_AD_25_LPSPI2_PCS0 }, \
77+
{ IOMUXC_GPIO_AD_26_LPSPI2_SOUT }, { IOMUXC_GPIO_AD_27_LPSPI2_SIN }, \
78+
{ 0 }, { 0 }, \
79+
{ 0 }, { 0 }, \
80+
{ 0 }, { 0 }, \
81+
{ 0 }, { 0 }, \
82+
{ 0 }, { 0 }, \
83+
{ 0 }, { 0 }, \
84+
{ 0 }, { 0 }, \
85+
{ 0 }, { 0 },
86+
87+
88+
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
89+
kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
90+
91+
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
92+
kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
93+
94+
// Define the mapping hardware I2C # to logical I2C #
95+
// phyBOARD-RT1170 I2C interfaces
96+
// LPI2C1 -> 0 (GPIO_AD_32/33) - EEPROM (SoM)
97+
// LPI2C2 -> 1 (GPIO_AD_18/19) - EEPROM + Accelerometer (Carrier)
98+
// LPI2C3 -> 2 (GPIO_DISP_B2_10/11) - Reserved (SoM)
99+
// LPI2C5 -> 3 (GPIO_LPSR_08/09, GPIO_AD_26/27) - Audio Codec + Accelerometer (Carrier)
100+
101+
#define MICROPY_HW_I2C_INDEX { 1, 2, 3, 5 }
102+
103+
#define IOMUX_TABLE_I2C \
104+
{ IOMUXC_GPIO_AD_32_LPI2C1_SCL }, { IOMUXC_GPIO_AD_33_LPI2C1_SDA }, \
105+
{ IOMUXC_GPIO_AD_18_LPI2C2_SCL }, { IOMUXC_GPIO_AD_19_LPI2C2_SDA }, \
106+
{ IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL }, { IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA }, \
107+
{ 0 }, { 0 }, \
108+
{ IOMUXC_GPIO_LPSR_08_LPI2C5_SDA }, { IOMUXC_GPIO_LPSR_09_LPI2C5_SCL }, \
109+
{ 0 }, { 0 },
110+
111+
#define MICROPY_PY_MACHINE_I2S (1)
112+
#define MICROPY_HW_I2S_NUM (1)
113+
#define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 }
114+
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx, kDmaRequestMuxSai3Rx, kDmaRequestMuxSai4Rx }
115+
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx, kDmaRequestMuxSai3Tx, kDmaRequestMuxSai4Tx }
116+
#define I2S_WM8960_RX_MODE (1)
117+
#define I2S_AUDIO_PLL_CLOCK (4U)
118+
#define DMAMUX DMAMUX0
119+
120+
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
121+
{ \
122+
.hw_id = _hwid, \
123+
.fn = _fn, \
124+
.mode = _mode, \
125+
.name = MP_QSTR_##_pin, \
126+
.iomux = {_iomux}, \
127+
}
128+
129+
#define I2S_GPIO_MAP \
130+
{ \
131+
I2S_GPIO(1, MCK, TX, GPIO_AD_17, IOMUXC_GPIO_AD_17_SAI1_MCLK), \
132+
I2S_GPIO(1, SCK, RX, GPIO_AD_19, IOMUXC_GPIO_AD_19_SAI1_RX_BCLK), \
133+
I2S_GPIO(1, WS, RX, GPIO_AD_18, IOMUXC_GPIO_AD_18_SAI1_RX_SYNC), \
134+
I2S_GPIO(1, SD, RX, GPIO_AD_20, IOMUXC_GPIO_AD_20_SAI1_RX_DATA00), \
135+
I2S_GPIO(1, SCK, TX, GPIO_AD_22, IOMUXC_GPIO_AD_22_SAI1_TX_BCLK), \
136+
I2S_GPIO(1, WS, TX, GPIO_AD_23, IOMUXC_GPIO_AD_23_SAI1_TX_SYNC), \
137+
I2S_GPIO(1, SD, TX, GPIO_AD_21, IOMUXC_GPIO_AD_21_SAI1_TX_DATA00), \
138+
}
139+
140+
// USDHC1 (SDCARD)
141+
#define MICROPY_PY_MACHINE_SDCARD 0
142+
#if MICROPY_PY_MACHINE_SDCARD
143+
#define USDHC_DUMMY_PIN NULL, 0
144+
#define MICROPY_USDHC1 \
145+
{ \
146+
.cmd = {GPIO_SD_B1_00_USDHC1_CMD}, \
147+
.clk = { GPIO_SD_B1_01_USDHC1_CLK }, \
148+
.cd_b = { USDHC_DUMMY_PIN }, \
149+
.data0 = { GPIO_SD_B1_02_USDHC1_DATA0 }, \
150+
.data1 = { GPIO_SD_B1_03_USDHC1_DATA1 }, \
151+
.data2 = { GPIO_SD_B1_04_USDHC1_DATA2 }, \
152+
.data3 = { GPIO_SD_B1_05_USDHC1_DATA3 }, \
153+
}
154+
#define USDHC_DATA3_PULL_DOWN_ON_BOARD (1)
155+
#endif
156+
157+
// Network definitions
158+
159+
// phyBOARD-RT1170 Dual Ethernet configuration
160+
// Port 0: KSZ8081 100Mbps RMII PHY on carrier board (PBA-C-26)
161+
// Port 1: DP83867 1Gbps RGMII PHY on phyCORE SoM
162+
163+
// Primary Ethernet (100M RMII) - KSZ8081 on carrier board
164+
#define ENET_PHY_ADDRESS (1) // KSZ8081 PHY address 001b
165+
#define ENET_PHY KSZ8081
166+
#define ENET_PHY_OPS phyksz8081_ops
167+
168+
// ENET RMII pin configuration - connected to carrier board KSZ8081
169+
#define IOMUX_TABLE_ENET \
170+
{ IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \
171+
{ IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \
172+
{ IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0, 0x06u }, \
173+
{ IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0, 0x02u }, \
174+
{ IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0, 0x02u }, \
175+
{ IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0, 0x06u }, \
176+
{ IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1, 0x03u }, \
177+
{ IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0, 0x06u }, \
178+
{ IOMUXC_GPIO_AD_33_ENET_MDIO, 0, 0x06u }, \
179+
{ IOMUXC_GPIO_AD_32_ENET_MDC, 0, 0x06u },
180+
181+
// Secondary Ethernet (1G RGMII) - DP83867 on phyCORE SoM
182+
#define ENET_1_PHY_ADDRESS (0)
183+
#define ENET_1_PHY DP83867
184+
#define ENET_1_PHY_OPS phydp83867_ops
185+
186+
// ENET_1G RGMII pin configuration - full RGMII pins for Gigabit operation
187+
#define IOMUX_TABLE_ENET_1 \
188+
{ IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, 0, 0x08U }, \
189+
{ IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, 0, 0x08U }, \
190+
{ IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, 0, 0x08U }, \
191+
{ IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, 0, 0x08U }, \
192+
{ IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, 0, 0x08U }, \
193+
{ IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, 0, 0x08U }, \
194+
{ IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, 0, 0x0CU }, \
195+
{ IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, 0, 0x0CU }, \
196+
{ IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, 0, 0x0CU }, \
197+
{ IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, 0, 0x0CU }, \
198+
{ IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, 0, 0x0CU }, \
199+
{ IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, 0, 0x0CU }, \
200+
{ IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, 0, 0x06u }, \
201+
{ IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, 0, 0x06u },
202+
203+
204+
// --- SEMC --- //
205+
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
206+
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
207+
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
208+
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
209+
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
210+
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
211+
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
212+
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
213+
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
214+
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
215+
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
216+
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
217+
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
218+
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
219+
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
220+
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
221+
222+
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
223+
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
224+
#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
225+
#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
226+
#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
227+
#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
228+
#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
229+
#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
230+
#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
231+
#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
232+
#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
233+
#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
234+
#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
235+
236+
#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
237+
#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
238+
#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
239+
#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
240+
#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
241+
#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
242+
#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_B1_28_SEMC_WE
243+
#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
244+
#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
245+
#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
246+
247+
#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
248+
249+
#define MIMXRT_IOMUXC_SEMC_DATA16 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
250+
#define MIMXRT_IOMUXC_SEMC_DATA17 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
251+
#define MIMXRT_IOMUXC_SEMC_DATA18 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
252+
#define MIMXRT_IOMUXC_SEMC_DATA19 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
253+
#define MIMXRT_IOMUXC_SEMC_DATA20 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
254+
#define MIMXRT_IOMUXC_SEMC_DATA21 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
255+
#define MIMXRT_IOMUXC_SEMC_DATA22 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
256+
#define MIMXRT_IOMUXC_SEMC_DATA23 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
257+
#define MIMXRT_IOMUXC_SEMC_DM02 IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
258+
259+
#define MIMXRT_IOMUXC_SEMC_DATA24 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
260+
#define MIMXRT_IOMUXC_SEMC_DATA25 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
261+
#define MIMXRT_IOMUXC_SEMC_DATA26 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
262+
#define MIMXRT_IOMUXC_SEMC_DATA27 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
263+
#define MIMXRT_IOMUXC_SEMC_DATA28 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
264+
#define MIMXRT_IOMUXC_SEMC_DATA29 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
265+
#define MIMXRT_IOMUXC_SEMC_DATA30 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
266+
#define MIMXRT_IOMUXC_SEMC_DATA31 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
267+
#define MIMXRT_IOMUXC_SEMC_DM03 IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
268+
#define MIMXRT_IOMUXC_SEMC_DQS4 IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4
269+
270+
#if MICROPY_PY_MACHINE_I2S
271+
#define MICROPY_BOARD_ROOT_POINTERS \
272+
struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM];
273+
#endif
274+
275+
// AUTOGENERATED by update.py from copier
276+
#define MICROPY_HW_USB_CDC_NUM (2)
277+
#define MICROPY_HW_USB_MSC (0)
278+
#define MICROPY_HW_USB_HID (0)
279+
280+
#define MICROPY_HW_USB_MANUFACTURER_STRING "PHYTEC"
281+
#define MICROPY_HW_USB_PRODUCT_HS_STRING "phyBOARD-RT1170 Development Kit"
282+
#define MICROPY_HW_USB_PRODUCT_FS_STRING "phyBOARD-RT1170 Development Kit"
283+
#define MICROPY_HW_USB_CONFIGURATION_HS_STRING "phyBOARD Config"
284+
#define MICROPY_HW_USB_INTERFACE_HS_STRING "phyBOARD Interface"
285+
#define MICROPY_HW_USB_CONFIGURATION_FS_STRING "phyBOARD Config"
286+
#define MICROPY_HW_USB_INTERFACE_FS_STRING "phyBOARD Interface"
287+
288+
#define MBOOT_USBD_MANUFACTURER_STRING "PHYTEC"
289+
#define MBOOT_USBD_PRODUCT_STRING "phyBOARD Boot"
290+
291+
// phyBOARD-RT1170 Development Kit hardware features
292+
293+
// Onboard EEPROM (M24C32 - 32Kbit)
294+
#define MICROPY_HW_EEPROM_I2C_BUS (0) // On LPI2C1 (SoM)
295+
#define MICROPY_HW_EEPROM_ADDR (0x50)
296+
297+
// Carrier board peripherals
298+
// Audio Codec: TLV320AIC3110 on LPI2C5 (I2C address: 0x18)
299+
// Accelerometer: ICM-40627 on LPI2C2 (I2C address: 0x6B)
300+
// CAN Interface: CAN3 (GPIO_LPSR_00/01)
301+
// RS-232 Serial: LPUART8 (GPIO_AD_02/03/04/05)
302+
// User Button: GPIO_AD_35
303+
// RGB LEDs: GPIO_AD_14 (red), GPIO_LPSR_13 (green)
304+
// microSD Card Slot: USDHC1
305+
// M.2 Connector (Key E): WiFi/Bluetooth modules
306+
307+
// Basic ADC channels available on connector
308+
#define MICROPY_HW_ADC_NUM_CHANNELS (16) // GPIO_AD domain pins

‎ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
MCU_SERIES = MIMXRT1176
2+
MCU_VARIANT = MIMXRT1176DVMAA
3+
MCU_CORE = _cm7
4+
5+
MICROPY_FLOAT_IMPL = double
6+
MICROPY_HW_FLASH_TYPE ?= qspi_nor_flash
7+
MICROPY_HW_FLASH_SIZE ?= 0x1000000 # 16MB
8+
MICROPY_HW_FLASH_RESERVED ?= 0x100000 # 1MB CM4 Code address space
9+
MICROPY_HW_FLASH_CLK = kFlexSpiSerialClk_100MHz
10+
MICROPY_HW_FLASH_QE_CMD = 0x31
11+
MICROPY_HW_FLASH_QE_ARG = 0x02
12+
# phyCORE SoM flash timing - use loopback from DQS pad for better signal integrity
13+
MICROPY_HW_FLASH_DQS = kFlexSPIReadSampleClk_LoopbackFromDqsPad
14+
15+
MICROPY_HW_SDRAM_AVAIL = 1
16+
MICROPY_HW_SDRAM_SIZE = 0x4000000 # 64MB
17+
18+
MICROPY_PY_LWIP = 1
19+
MICROPY_PY_SSL = 1
20+
MICROPY_SSL_MBEDTLS = 1
21+
MICROPY_PY_OPENAMP = 1
22+
MICROPY_PY_OPENAMP_REMOTEPROC = 1
23+
24+
FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
25+
26+
CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 \
27+
-DMIMXRT117x_SERIES \
28+
-DENET_ENHANCEDBUFFERDESCRIPTOR_MODE=1 \
29+
-DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \
30+
-DUSB1_BASE=USB_OTG1_BASE \
31+
-DUSB2_BASE=USB_OTG2_BASE

0 commit comments

Comments
 (0)